On-Chip Debug Architecture for Multicore Processor

Park, Hyeongbae

doi:10.4218/etrij.11.0111.0172

Cited by 1 publication

(11 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To verify the EA-MOCD block, we test all the debug functions at the desired breakpoint, such as breakpoint programming and detection, debug/resume, single-step, register read/write, memory read/write, and variable read/write. Table 2 shows the comparison result of the gate count between the proposed EA-MOCD and the MOCD introduced by [14]. We perform the synthesis procedure using a commercial 90-nm CMOS cell library.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Figure 4 shows the detailed view of the extended For the debugging of a multicore processor, we added several user defined JTAG instructions without any additional bit length of JTAG instruction register. While maintaining full IEEE 1149.1 compliance, the extended JTAG block uses only one TAP controller and JTAG connection to control and debug all JTAG-based IPs integrated in the multicore processor embedding the EA-MOCD.The EA-MOCD supports the monitoring mode debugging instead of the MOCD's run-stop-type described by [14], and it does not use the inserting instruction method. So the scan chains of the EDU blocks are not necessary in our proposed debug architecture.…”

mentioning

confidence: 99%

“…Therefore, to effectively debug such multicore processor systems, cross breakpoint mechanisms are needed [25]-[28]. The MDSU does not include the clock controller module introduced by [14] because the EA-MOCD uses the monitoring mode debugging instead of the run-stop mode. Thus, even though there are two clock sources (system clock, JTAG tck clock), the EA-MOCD uses the individual clock domains that are different from the complex clock domains of the MOCD.…”

mentioning

confidence: 99%

“…The comparator module is designed to program and detect the breakpoint occurrence. The CFD module is a coprocessor used for transferring debug commands and information between the processor core and software debugger.In part A of subsection III, we will briefly introduce the comparator module, studied by the researchers in [14]. In part B of subsection III.3, we will concretely describe the CFD, which is the key of the monitoring mode debugging method.…”

mentioning

confidence: 99%

“…In this aspect, the EA-MOCD has disadvantages. However, it is still superior to the MOCD regarding gate count and execution cycles.To adapt the MOCD to a new multicore processor, we must modify the processor cores slightly, as demonstrated by [14]. It is also necessary to modify the GDBstub software interface module because the MOCD uses the inserting instruction scheme for debugging while other processor cores use a different instruction set.…”

mentioning

confidence: 99%

See 4 more Smart Citations

Easily Adaptable On-Chip Debug Architecture for Multicore Processors

Xu¹,

Park²,

Jung³

et al. 2013

ETRI J

Self Cite

View full text Add to dashboard Cite

Jing-Zhe Xu et al. 301Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time-consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on-chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run-stop mode debugging. Compared with the debug architecture that supports the run-stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on-chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.Keywords: JTAG, on-chip debugger, on-chip debug architecture, multicore processor debugging, monitoring mode debugging. Manuscript received July 18, 2012; revised Sept. 17, 2012; accepted Oct. 1, 2012 I. IntroductionToday, the multicore processor is more attractive than the single-core processor and widely used in embedded systems. However, there are many problems that need to be solved, such as with interconnection, cache coherency, scheduling, synchronization, the programming model, application, and so on [1]- [3]. In addition to these problems, the debugging of a multicore processor is also a challenging task.Some bugs of a system on chip (SoC) or its application programs appear only when executing the applications in real cases. So, having a debug unit to support debug functions is very necessary. Because of the dramatic increase in processor performance and the intrinsic lack of observability and controllability in multicore processors, an outside debug unit can no longer provide efficient debug capabilities, for example, in-circuit emulators or ROM monitors [4], [5]. In recent years, most processors employ an on-chip debug method that embeds a debug support logic into the target processor. The on-chip debug logic embedded in a processor works by interconnecting with a software debugger. It can allow the software developer to directly control the processor operation and examine the internal status, registers, and memories for debugging.On-chip debug functionalities can be classified into three types, based on the supported debug method. The first type supports a run-stop method that stops the processor core on a desired breakpoint to inspect the core ' Developing an on-chip-based processor debugger could be a difficult and complicated job that requires considerable time and effort. Therefore, easily adaptable and flexible on-chip debug architecture is needed for small companies and academic groups that develop their own customized processor cores for ge...

show abstract

Section: Implementation Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 3 more Smart Citations