On-Chip Clocking of Nanomagnet Logic Lines and Gates

Alam, M.T.; Kurtz, S.; Siddiq, Mohammad Abu Jafar; Niemier, Michael; Bernstein, Gary H.; Hu, Xiaobo Sharon; Porod, Wolfgang

doi:10.1109/tnano.2011.2169983

Cited by 52 publications

(41 citation statements)

References 35 publications

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“…1d and Supplementary Fig. 1 ) terminates each chain to stabilize the final nanomagnet after successful signal propagation 8 ( Supplementary Note 1 ). Static magnetic contrast images taken after triggering a single clock pulse are detected by X-ray magnetic circular dichroism (XMCD) 29 (see Methods section), which is sensitive to the proportion of the magnetization vector parallel to the propagation direction of the incident X-rays (along as shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…To perform multiple, successive logic operations, the entire NML architecture (chains and majority logic gates) must be reinitialized after each operation. This resetting process is known as clocking, and in this work we use pulsed nanosecond on-chip magnetic fields 8 to drive the magnetization of all nanomagnets in a chain to saturation along their magnetic hard axes. This places each magnet in an energetically unstable (null) state that, upon removal of the clock field, becomes coupled to a nearest-neighbour magnet by the dipolar fields.…”

mentioning

confidence: 99%

“…Previous studies of NML have incorporated static magnetic imaging after clocking chains and assumed corrected signal propagation based on the final observed output state 2 5 8 12 13 14 20 22 23 24 . In this work, we use an X-ray-based imaging technique with 100 ps resolution to directly observe the signal propagation dynamics in chains immediately after clocking.…”

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confidence: 99%

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Sub-nanosecond signal propagation in anisotropy-engineered nanomagnetic logic chains

Nowakowski

Carlton

et al. 2015

Nat Commun

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Energy efficient nanomagnetic logic (NML) computing architectures propagate binary information by relying on dipolar field coupling to reorient closely spaced nanoscale magnets. Signal propagation in nanomagnet chains has been previously characterized by static magnetic imaging experiments; however, the mechanisms that determine the final state and their reproducibility over millions of cycles in high-speed operation have yet to be experimentally investigated. Here we present a study of NML operation in a high-speed regime. We perform direct imaging of digital signal propagation in permalloy nanomagnet chains with varying degrees of shape-engineered biaxial anisotropy using full-field magnetic X-ray transmission microscopy and time-resolved photoemission electron microscopy after applying nanosecond magnetic field pulses. An intrinsic switching time of 100 ps per magnet is observed. These experiments, and accompanying macrospin and micromagnetic simulations, reveal the underlying physics of NML architectures repetitively operated on nanosecond timescales and identify relevant engineering parameters to optimize performance and reliability.

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Sub-nanosecond signal propagation in anisotropy-engineered nanomagnetic logic chains

Nowakowski

Carlton

et al. 2015

Nat Commun

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“…1c). [12] proposed CMOS compatible clocks that have been (i) fabricated [13], (ii) used to switch the state of individual magnetic islands [13], and (iii) used to re-evaluate line and gate structures with new inputs [14]. Looking to larger systems, parallel ensembles of magnets over a given wire (Fig.…”

Section: Field-driven Clockingmentioning

confidence: 99%

Making non-volatile nanomagnet logic non-volatile

Dingler

Kurtz

Niemier

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Field-coupled nanomagnets can offer significant energy savings at iso-performance versus CMOS equivalents. Magnetic logic could be integrated with CMOS, operate in environments that CMOS cannot, and retain state without power. Clocking requirements lead to inherently pipelined circuits, and high throughput further improves application-level performance. However, bit conflictsthat will occur in defect free, pipelined ensembles -can make non-volatile logic volatile. Assuming a field-based clock, we present hardware designs to improve steady state non-volatility, and explain how design enhancements could increase clock energy. We then suggest materials-related design levers that could simultaneously deliver non-volatility and low clock energy.

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“…With clock overheads, projections indicate that iNML circuits could be more energy efficient than low-power CMOS equivalents without performance losses [1]. Copper wires clad with ferromagnetic material on the sides and bottom, have been fabricated and used to re-evaluate line and gate ensembles [2]. Fig.…”

Section: Introductionmentioning

confidence: 99%