On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits

Kim, Kyung Ki; Wang, Wei; Choi, Ken

doi:10.1109/tcsii.2010.2067810

Cited by 93 publications

(42 citation statements)

References 7 publications

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“…We can capture the aging effect by connecting the ROs and circuits to the same power rails so that the ROs and the circuits are turned on and off together. Alternatively, more sophisticated aging sensors can be used to quantify the additional voltage margin to guardband for circuit aging [12]. Our ongoing work pursues a proof of concept for application of our proposed methodology to multi-V th design, as well as validation of the methodology across different temperatures.…”

Section: Resultsmentioning

confidence: 99%

Tunable sensors for process-aware voltage scaling

Chan

Kahng

2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-VLSI circuits usually allocate excess margin to account for worst-case process variation. Since most chips are fabricated at process conditions better than the worst-case corner, adaptive voltage scaling (AVS) is commonly used to reduce power consumption whenever possible. A typical AVS setup relies on a performance monitor that replicates critical paths of the circuit to guide voltage scaling. However, it is difficult to define appropriate critical paths for an SoC which has multiple operating modes and IPs. In this paper, we propose a different methodology for AVS which matches the voltage scaling characteristics of a circuit rather than the delays of critical paths. This fundamental change in monitoring strategy simplifies the monitoring circuitry as well as the calibration flow of conventional monitoring methods. To enable the proposed methodology, we study voltage scaling characteristics of digital circuits. Based on our analyses, we develop design guidelines as well as design monitoring circuits which have tunable voltage scaling characteristics. Our experimental results show that this methodology can be used for AVS with a simplified calibration flow.

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Section: Resultsmentioning

confidence: 99%

Tunable sensors for process-aware voltage scaling

Chan

Kahng

2012

Proceedings of the International Conference on Computer-Aided Design

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“…Circuit simulations based on the TSMC 65 nm technology library suggests that our designs accurately capture the aging phenomenon and have low sensitivity 0.29 mV/°C to temperature and 0.24 mV/mV to voltage, respectively, when compared with 0.51 mV/°C for NBTI sensor and 0.325 mV/°C for HCI sensor from prior work [7]. Fig.…”

Section: Introductionmentioning

confidence: 84%

Variation tolerant on-chip degradation sensors for dynamic reliability management systems

Wang

Enachescu

Cotofana

et al. 2012

Microelectronics Reliability

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“…The recovery procedure of our HP approach is repeated till a maximum of M times given by: (12) where the symbols are the same as those in Eq. 6.…”

Section: Hp Recovery Phasementioning

confidence: 99%

“…Several aging sensors have been proposed so far to monitor NBTI degradation (e.g., those in [9,10,11,12,4,8,7,13,14]). In [10,11,12], the sensors are implemented by ring-oscillators allowing to identify performance degradation by monitoring possible changes in their oscillation frequency.…”

Section: Introductionmentioning

confidence: 99%