On broad-side delay test

Savir, J.; Patil, S.

doi:10.1109/92.311647

Cited by 66 publications

(50 citation statements)

References 10 publications

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“…Unfortunately, the architectural limitations of scan DFT restrict the V2 pattern that can be applied during timing tests. Two-pattern scan tests operate in either the Launch-on-Capture (LOC) [5] or Launchon-Shift (LOS) [6] modes. However, at-speed LOS timing tests require a fast scan control (enable) signal.…”

Section: Introductionmentioning

confidence: 99%

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

Zou

Han

Singh

2014

2014 IEEE 23rd Asian Test Symposium

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Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant fraction of the timing defects, including many unique failures that are missed by LOC test. This suggests the use of combined LOC and LOS test to increase the TDF coverage beyond that attainable by LOC tests alone. However, to maximize the detection of real delay defects, the LOS tests must be applied at the fastest possible speed (up to the functional clock rate) within the timing limitations of the scan enable. To support such testing, in this paper we present the first test technique to reliably evaluate the switching speed of the scan enable signal. This can vary significantly for individually manufactured instances of the same design due to normal process variations at advanced technology nodes, amplified by near quadratic delays in the long interconnect lengths of this broadcast signal. Once the scan enable speed is determined, LOS tests can be applied at the fastest, most effective speed. Furthermore, the availability of this effective low cost LOS test capability also facilitates the partitioning of the scan flip flops through the use of multiple scan enable signals that apply the delay test in mixed LOS and LOC modes in the different partitions. We show that the use of only two scan enable signals in such an approach can significantly increase TDF test coverage, and raise it very close to the highest possible that is achievable only by enhanced scan.

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Section: Introductionmentioning

confidence: 99%

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

Zou

Han

Singh

2014

2014 IEEE 23rd Asian Test Symposium

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“…Under broadside tests [2], the state s 2 of the second pattern is obtained by latching the next-state obtained under the first pattern, and using it as part of the second pattern. Thus, s 2 is determined from s 1 and v 1 , and the circuit is switched from scan mode to functional mode during the application of the first pattern.…”

Section: Introductionmentioning

confidence: 99%

On Common-Mode Skewed-Load and Broadside Tests

Pomeranz

Reddy

Kundu

2008

21st International Conference on VLSI Design (VLSID 2008)

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Two-pattern tests for delay faults in standard scan circuits can be of one of two types: skewed-load or broadside. Each type of tests creates different conditions during test application due to the different way in which scan mode and functional mode are interleaved. Therefore, tests that are applicable both as skewed-load tests and as broadside tests are useful for comparing the two types of tests with respect to properties such as defect coverage or overtesting. In this work we investigate the possibility of generating tests that are applicable under both test application schemes. We refer to two-pattern tests that are applicable as both skewed-load and broadside tests as common −mode tests. We show that most benchmark circuits have sufficient numbers of common-mode tests to make them an interesting class of tests. Moreover, we show that the use of multiple scan chains increases the number of common-mode tests.

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“…This also holds for launch on capture (LOC) resp. broadside transition-delay fault simulation [Savir and Patil 1994]. For these two cases, the input to a sequential element is directly connected to the corresponding input in the next time frame.…”

Section: Combinational Expansion Of the Sequential Circuitmentioning

confidence: 99%

Exact Logic and Fault Simulation in Presence of Unknowns

Erb

Kochte

Sauer

et al. 2014

ACM Trans. Des. Autom. Electron. Syst.

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Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit and a pessimistic underestimation of fault coverage. This work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation that are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected, or possibly detected. The pessimism with respect to unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that, by accurate analysis, the number of detected faults can be significantly increased without increasing the test-set size. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by ACM.c 2014 ACM. Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Logic and fault simulation are essential techniques in electronic design automation. The accuracy of standard simulation algorithms is compromised by unknown or X-values. This results in a pessimistic overestimation of X-valued signals in the circuit, and a pessimistic underestimation of fault coverage. A Exact Logic and Fault Simulation in Presence of UnknownsThis work proposes efficient algorithms for combinational and sequential logic as well as for stuck-at and transition-delay fault simulation which are free of any simulation pessimism in presence of unknowns. The SAT-based algorithms exactly classifiy all signal states. During fault simulation, each fault is accurately classified as either undetected, definitely detected or possibly detected.The pessimism w. r. t. unknowns present in classic algorithms is thoroughly investigated in the experimental results on benchmark circuits. The applicability of the proposed algorithms is demonstrated on larger industrial circuits. The results show that by accurate analysis the number of de...

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On broad-side delay test

Cited by 66 publications

References 10 publications

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

On Common-Mode Skewed-Load and Broadside Tests

Exact Logic and Fault Simulation in Presence of Unknowns

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