On bounding response times under software transactional memory in distributed multiprocessor real-time systems

Fahmy, Sonia; Ravindran, Binoy; Jensen,

doi:10.1109/date.2009.5090753

Cited by 13 publications

(7 citation statements)

References 12 publications

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“…Prior work on the schedulability analysis of STM has been done by Fahmy et al ( [6], [7]), Sarni et al [16] and Schoeberl et al [19]. These previous methods extend techniques of the preemptive execution model for computing approximate response time bounds in STM.…”

Section: Related Workmentioning

confidence: 98%

“…It extends finite state automata by using clocks, which allow for conditional state transitions. In ( [7], [8]) the notion of Extended Timed Automata (ETA) where states represent the execution of tasks, has been presented. ETA has become the standard for representing schedulability models using Timed Automata, and is also used in this work.…”

Section: Timed Automatamentioning

confidence: 99%

“…Several TA encodings that determine response time in the preemptive and non-preemptive models of execution have been presented ([1], [7], [8], [10]). While these automata are useful and offer an alternative, they are not the first choice since several state-of-the-art polynomial time algorithms already exist for exact schedulability analysis of preemptive and non-preemptive execution models.…”

Section: Introductionmentioning

confidence: 99%

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Schedulability Analysis of Transactions in Software Transactional Memory Using Timed Automata

Belwal

Cheng

2011

2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications

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1 -Software Transactional Memory (STM) is a mechanism for controlling access to shared resources in memory using an abort-restart preemption model for tasks which share data objects. This execution model of STM is different from the classical preemptive or non-preemptive models and currently the only method to determine schedulability is through an exhaustive search through the state space of all release scenarios of higher priority tasks. The existing method is costly and scales exponentially with the number of tasks making its use limited in practical situations. Timed Automata has been proven as an expressive formalism for time based systems. This paper presents a methodology for developing Timed Automata encodings for the schedulability analysis of STM systems. We validate our models using the model checker UPPAAL, and show that Timed Automata offers an efficient alternative for schedulability analysis in real-time STM.

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Section: Related Workmentioning

confidence: 98%

Section: Timed Automatamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Schedulability Analysis of Transactions in Software Transactional Memory Using Timed Automata

Belwal

Cheng

2011

2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications

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“…Past research on real-time CM have proposed resolving transactional contention using dynamic and fixed priorities of parent threads, resulting in Earliest-Deadline-First-based CM (ECM) and Rate Monotonic Assignment-based CM (RCM), respectively [7][8][9]. These works show that, ECM and RCM, when used with the Global EDF (G-EDF) and Global RMA (G-RMA) multicore schedulers, respectively, achieve higher schedulability than lock-free synchronization techniques only under some ranges for the maximum atomic section length.…”

Section: Introductionmentioning

confidence: 99%

STM concurrency control for embedded real-time software with tighter time bounds

El-Shambakey

Ravindran

2012

Proceedings of the 49th Annual Design Automation Conference

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We consider software transactional memory (STM) concurrency control for multicore real-time software, and present a novel contention manager (CM) for resolving transactional conflicts, called length-based CM (or LCM). We upper bound transactional retries and response times under LCM, when used with G-EDF and G-RMA schedulers. We identify the conditions under which LCM outperforms previous real-time STM CMs and lock-free synchronization. Our implementation and experimental studies reveal that G-EDF/LCM and G-RMA/LCM have shorter or comparable retry costs and response times than other synchronization techniques.

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“…Besides complex hardware support for rolling back and comparing transactions, we see an additional issue. This issue concerns predictability, which is important in the design of MPSoCs, but predictable speculative execution appears to be challenging [6].…”

Section: Figure 1: Mpsoc With a Noc And Shared Memorymentioning

confidence: 99%

A tuneable software cache coherence protocol for heterogeneous MPSoCs

Ophelders

Bekooij

Corporaal

2009

Proceedings of the 7th IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis

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In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing hardware cache coherence protocols are less suitable for MPSoCs because many off-the-shelf processors used in MPSoCs do not support these protocols. Furthermore, these protocols typically rely on global visibility and serialization of writes which does not match well with the parallel pointto-point communication provided by a NoC. Therefore, we propose a software cache coherence protocol, which can be applied in a heterogeneous MPSoC with a NoC. The software cache coherence protocol relies on explicit synchronization in the software. More specifically, caches are guaranteed to be coherent according to the Release Consistency model, on top of which we have implemented the standard Pthreads communication library. Heterogeneous MPSoCs with off-the-shelf processors can easily be supported, because processors are only required to provide cache control operations, e.g., clean and invalidate. All cache coherence operations are interruptible and do not impact the execution of tasks on other processors, therefore this protocol is suitable for predictable MPSoCs. Our software cache coherence protocol is implemented on an ARM926EJ-S MPSoC which is mapped on an FPGA. From experiments we conclude that the protocol overhead is low for the applications taken from the SPLASH-2 benchmark set. For these applications we observed a speedup between 1.89 and 2.01 on the two processor MPSoC.

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On bounding response times under software transactional memory in distributed multiprocessor real-time systems

Cited by 13 publications

References 12 publications

Schedulability Analysis of Transactions in Software Transactional Memory Using Timed Automata

Schedulability Analysis of Transactions in Software Transactional Memory Using Timed Automata

STM concurrency control for embedded real-time software with tighter time bounds

A tuneable software cache coherence protocol for heterogeneous MPSoCs

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