Offset Trench Isolation

Abstract

Feasibility of a new, recessed isolation technique that utilizes an offset, shallow trench in combination with thermal oxidation for achieving near zero final encroachment with excellent planarity is demonstrated. Etch of the shallow trench is offset from the original hardmask by an oxide sidewall spacer. After trench etch, HF is used to remove the hardmask oxide and sidewall spacers and to form a cavity which is self-aligned to the nitride edge. Exposed silicon regions are then reoxidized and encapsulated with polysilicon. Field oxide is then grown. The final field oxide profile exhibits steep sidewall angles without inducing substrate defects as evidenced by low diode leakage. Other isolation sensitive device parametrics such as gate oxide quality and metal oxide semiconductor field effect transistor threshold voltage stability are presented and exhibit good characteristics.Advanced isolation techniques, while varied in concept and complexity, are typically intended to provide low final active area encroachment, recessing of oxide, low diode leakage, excellent gate oxide quality and stable metal oxide semiconductor field effect transistor (MOSFET) threshold voltage vs. transistor width. ~-1~ The approaches for realizing such an isolation may be broadly divided into three categories: recessed thermal oxidation/-7 trench and fill, 8-1~ and selective silicon. 14 Recessed thermal oxidation techniques include a shallow trench etch in the field regions prior to field oxidation. The ensuing field oxidation thus initiates below the original substrate surface, and the volume expansion associated with the oxidation gives a near planar isolation. Unfortunately, locating the shallow trench immediately adjacent to the oxidation mask edge allows excessive encroachment for device technologies below 0.50 ~m. Trench and fill isolation approaches also include a shallow trench located immediately adjacent to the hardmask, however; the trench is filled using a deposited oxide tetraethylorthosilicate [(TEOS) source gas] and after oxide deposition, a separate planarization process is accomplished. While this technique gives excellent ZOO nm Oxide Hardmask , / 140 nm Nitride ,~50 nm Pad Oxide gubstrate 1 (a) 1 O0 nm Oxide Sidewall Spacer Substrate I (b)isolation planarity, it is prone to poor gate oxide integrity and thermal stress-induced defect formation in the substrate. 1~' 13 Selective silicon isolation alternatives have not yet received extensive consideration as they are subject to silicon faceting, incomplete selectivity, and high process complexity. 1~ Offset trench isolation is introduced as an alternative trench-based isolation technique. Submicron isolation structures fabricated utilizing this technique are examined for defect formation, encroachment, and gate oxide quality as these regions represent the most demanding feasibility test. Offset Trench Process FlowThe offset trench process flow is shown in Fig. 1. After growing 50 nm of pad oxide, 140 nm of LPCVD nitride and 200 nm of hardmask oxide are sequentially deposit...