Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis

Xu, Yongsheng; Belostotski, Leonid; Haslett, J.W.

doi:10.1109/newcas.2011.5981309

Cited by 16 publications

(5 citation statements)

References 4 publications

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“…Since we used Xu et al's comparator at 4 GHz [36], we configured the networks for an average spike accumulation period (t f ire ) of 0.8 ns and an output spike duration (t spike ) of 0.2 ns. Thus, the 10 average output spikes occur roughly once every t f ire + t spike =1 ns.…”

Section: Models Used For Power and Accuracy Comparisonsmentioning

confidence: 99%

Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture

Woods

Teuscher

2019

IEEE Trans. Neural Netw. Learning Syst.

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Memristive crossbars have become a popular means for realizing unsupervised and supervised learning techniques. In previous neuromorphic architectures with leaky integrate-andfire neurons, the crossbar itself has been separated from the neuron capacitors to preserve mathematical rigor. In this work, we sought to design a simplified sparse coding circuit without this restriction, resulting in a fast circuit that approximated a sparse coding operation at a minimal loss in accuracy. We showed that connecting the neurons directly to the crossbar resulted in a more energy-efficient sparse coding architecture, and alleviated the need to pre-normalize receptive fields. This work provides derivations for the design of such a network, named the Simple Spiking Locally Competitive Algorithm, or SSLCA, as well as CMOS designs and results on the CIFAR and MNIST datasets. Compared to a non-spiking, non-approximate model which scored 33 % on CIFAR-10 with a single-layer classifier, this hardware scored 32 % accuracy. When used with a state-ofthe-art deep learning classifier, the non-spiking model achieved 82 % and our simplified, spiking model achieved 80 %, while compressing the input data by 92 %. Compared to a previously proposed spiking model, our proposed hardware consumed 99 % less energy to do the same work at 21 × the throughput. Accuracy held out with online learning to a write variance of 3 %, suitable for the often-reported 4-bit resolution required for neuromorphic algorithms; with offline learning to a write variance of 27 %; and with read variance to 40 %. The proposed architecture's excellent accuracy, throughput, and significantly lower energy usage demonstrate the utility of our innovations.

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Section: Models Used For Power and Accuracy Comparisonsmentioning

confidence: 99%

Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture

Woods

Teuscher

2019

IEEE Trans. Neural Netw. Learning Syst.

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“…In the second phase, the pre-amplifier output nodes up to the power supply voltage level. Also, the comparator offset can be cancelled in this phase [10][11]. Consequently, the comparator offset effect has not been considered in this paper.…”

Section: Structurementioning

confidence: 99%

Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

Dashtbayazi¹,

Sabaghi

Marjani³

2015

JEEE

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“…For example, based on [20, Table I], the power consumption of a typical Zero-IF RX is 122.35mW. This value is decreased as 22.59 mW in a one-bit SDRX with a 90 μW/5GHz comparator [7].…”

Section: A One-bit Sdr Rx For Large-scale Mimomentioning

confidence: 99%

“…In this paper, software defined radio receivers (SDRXs) with one-bit ADC (also named as comparator) are designed for the BS. They have ultra-low power and ultra-low cost because many analog devices, such as RF synchronizer, low-pass filters, etc., are saved, and there exist many low-power comparators [7], [8], [21] which can satisfy the sampling requirement in SDR.…”

Section: Introductionmentioning

confidence: 99%

Multiuser detection for uplink large-scale MIMO under one-bit quantization

Wang

Jing

2014

2014 IEEE International Conference on Communications (ICC)

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In large-scale Multiple Input Multiple Output (MI-MO), the number of Base Station (BS) antennas reaches tens even hundreds. If so many radio frequency front-ends adopt the classical receivers, their cost and power consumption during the receiving mode would increase quickly. Consequently, we exploit one-bit Analog Digital Convertor (ADC) to design low-cost and low-power software defined radio receivers for the BS. However, the new problem is how the BS fulfills Multiuser Detection (MUD) based on the one-bit baseband data. Based on the Message Passing De-Quantization (MPDQ) algorithm, an iterative multiuser detector is constructed. Its convergence properties is analyzed by the State Evolution (SE), and then its complexity is proved to be one order of magnitude smaller than that of the Minimum Mean Square Error (MMSE) detector. Simulation results show that the proposed detector outperforms MMSE. Finally, the proposed detector with matrix-vector multiplications is suitable for hardware implementation.

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Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis

Cited by 16 publications

References 4 publications

Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture

Fast and Accurate Sparse Coding of Visual Stimuli With a Simple, Ultralow-Energy Spiking Architecture

Dynamic Comparator with Using Negative Resistance and CMOS Input Pair Strategies in FS =4MHz-10GHz

Multiuser detection for uplink large-scale MIMO under one-bit quantization

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