Offset assignment using simultaneous variable coalescing

Abstract

The generation of efficient addressing code is a central problem in compiling for processors with restricted addressing modes, like digital signal processors (DSPs). Offset assignment (OA) is the problem of allocating scalar variables to memory, so as to minimize the need of addressing instructions. This problem is called simple offset assignment (SOA) when a single address register is available, and general offset assignment (GOA) when more address registers are used. This paper shows how variables' liveness information can be used to dramatically reduce the addressing instructions required to access local variables on the program stack. Two techniques that make effective use of variable coalescing to solve SOA and GOA are described, namely coalescing SOA (CSOA) and coalescing GOA (CGOA). In addition, a thorough comparison between these algorithms and others described in the literature is presented. The experimental results, when compiling Me-diaBench benchmark programs with the LANCE compiler, reveal a very significant improvement of the proposed techniques over the other available solutions to the problem.

Solving the simple offset assignment problem as a traveling salesman

“…The approach to group such variables is called variable coalescing. Ottoni et al [23] presented a first heuristic which was followed by another one by Salamy and Ramanujam [26]. Recently, the latter authors also developed an ILP formulation for offset assignment with variable coalescing [27].…”

Optimal general offset assignment

“…A different idea named variable coalescing is to share storage locations among variables whose lifetimes do not overlap. Ottoni et al [19] presented a first heuristic which was followed by another one and an ILP formulation by Salamy and Ramanujam [23,24]. However, for the exact approach again the instances solved had to be restricted to sizes of about 30 variables due to the running time of the solver.…”

Optimal address register allocation for arrays in DSP applications

“…For instance, references r1, r3, and r5 in Figure 1(c) are addressed using address register AR1 due to the path cover (r1 r3 r5) and references r2, r4, and r6 are covered by AR2 whereas reference r7 is covered by AR3. Several others [4], [13], [3], [15], [16], [19], [22], [14] have addressed this problem in the case of scalar based embedded applications.…”