NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Poremba, Matthew; Zhang, Tao; Xie, Yuan

doi:10.1109/lca.2015.2402435

Cited by 201 publications

(64 citation statements)

References 8 publications

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“…Both are focused on improving the reliability and lifetime of the 4LC PCM. We conducted a system-level simulation using Gem5 [30] and NVMain 2.0 [31] with 21 benchmarks from the SPEC CPU 2006 benchmark suite [32]. To eliminate the effect of cold cache misses, which impedes accurate performance evaluation, we first executed 100 million instructions for each benchmark.…”

Section: Simulation Environmentmentioning

confidence: 99%

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

et al. 2020

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Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.Electronics 2020, 9, 626 2 of 16 MLC PCM as the main memory or a storage class memory (SCM). Indeed, various methods have been introduced to use the MLC technology effectively when targeting PCM as the main memory [7][8][9][10][11][12][13][14][15].For reliable data retention, and for coping with the reduced sensing margin, iterative write-and-verify (read) operations must be executed for each memory cell in the MLC PCM, which deteriorates its lifetime and performance. In addition, MLC PCM suffers from a significantly higher soft error rate (SER) when compared to DRAM. This is mainly caused by the resistance drift phenomenon that blurs the sensing boundary between adjacent states. The use of error-correction code (ECC) is a common technique in reducing the SER of MLC PCM; however, it adversely affects the performance and area efficiency.Scrubbing can help diminish the SER by reading, detecting, and correcting errors by utilizing the parity bit check and writing them back into the cell [16]. The shorter the scrubbing period, the lower the SER. However, frequent scrubbing accelerates the wearing out of PCM. In [10], the authors proposed an efficient scrubbing mechanism that could flexibly determine the scrubbing period considering the error-vulnerable patterns. In addition, recent studies focused on designing reliable 4LC PCM to mitigate the overhead caused by ECC and scrubbing, by expelling the most error-vulnerable pattern [7][8][9][10][11][12].Obviously, long ECC decoding latency is a significant bottleneck in achieving a high-performance memory system [17]. Moreover, complicated ECC algorithms are unacceptable in the MLC PCM based main memory ...

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Section: Simulation Environmentmentioning

confidence: 99%

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

et al. 2020

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“…The system level analysis is carried out by combining two modeling and simulation tools: gem5 [11] and NVMain Design, Automation And Test in Europe (DATE 2018) [12]. From input parameters characterizing a given system configuration, these tools are co-simulated in order to produce execution statistics including execution time, memory transactions and related latencies, power/energy consumption.…”

Section: System Level Analysismentioning

confidence: 99%

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Perumkunnil

Rock

Hartmann

et al. 2018

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Current main memory organizations in embedded and mobile application systems are DRAM dominated. The everincreasing gap between today's processor and memory speeds makes the DRAM subsystem design a major aspect of computer system design. However, the limitations to DRAM scaling and other challenges like refresh provide undesired trade-offs between performance, energy and area to be made by architecture designers. Several emerging NVM options are being explored to at least partly remedy this but today it is very hard to assess the viability of these proposals because the simulations are not fully based on realistic assumptions on the NVM memory technologies and on the system architecture level. In this paper, we propose to use realistic, calibrated STT-MRAM models and a well calibrated cross-layer simulation and exploration framework, named SEAT, to better consider technologies aspects and architecture constraints. We will focus on general purpose/mobile SoC multicore architectures. We will highlight results for a number of relevant benchmarks, representatives of numerous applications based on actual system architecture. The most energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 27% at the cost of 2x the area and the least energy efficient STT-MRAM based main memory proposal provides an average energy consumption reduction of 8% at the around the same area or lesser when compared to DRAM.

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“…Since our technique determines pipeline widths depending on the memory-intensiveness (or computation-intensiveness), our technique can dynamically control the memory bandwidth pressure, which eventually results in a positive impact on system-wide performance. [18]. For thermal evaluation, we use HotSpot [19] architectural thermal modeling tool.…”

Section: Hardware and Runtime Supportmentioning

confidence: 99%

3D die-stacked DRAM thermal management via task allocation and core pipeline control

Yoon

Shim

Moon

et al. 2018

IEICE Electron. Express

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A major hurdle to adopt 3D stacked DRAM is a thermal problem particularly when the DRAM dies are stacked above the processor dies. Exacerbated thermal problems in DRAM cause another problem which increases refresh rates to ensure data integrity of DRAM cells. In this paper, we propose two efficient techniques to address the thermal problem in 3D die-stacked DRAM by suppressing adverse thermal impacts from the processor die. Our thermal-aware task mapping technique allocates tasks to cores by considering computation-intensiveness of the workloads to minimize thermal interactions. The workload-aware core pipeline control technique adjusts pipeline widths (fetch and issue widths) of processor cores considering the workload characteristics. By adopting our proposed techniques, system-wide energy consumption is reduced by 7.6% while improving performance by 0.4% on average, thanks to the reduced pipeline widths and refresh rates. In terms of temperature, our techniques reduce the number of DRAM banks which exceed 85 degree Celsius by 92.8%, on average.

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NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Cited by 201 publications

References 8 publications

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

3D die-stacked DRAM thermal management via task allocation and core pipeline control

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