NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

Kim, S.; Ishii, Masatoshi; Lewis, S.H.; Perri, T.; BrightSky, M.; Kim, W.; Jordan, Richard C.; Burr, Geoffrey W.; Sosa, Norma; Ray, A.; Han, Jin‐Ping; Miller, Christopher P.; Hosokawa, Kohji; Lam, C.

doi:10.1109/iedm.2015.7409716

Cited by 169 publications

(104 citation statements)

References 7 publications

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“…By using the dummy weight, we can make the absolute values of β ± identical (β = 0), and we define Also, according to Eqs. (12) and (13), the absolute values of θ + and θ − can be the same, and θ + + θ − = 0. Therefore, Eq.…”

Section: Time-domain Weighted-sum Calculation With Different-signed Wmentioning

confidence: 93%

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Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Wang

Tamukoh

Matsukawa

2016

Neural Information Processing

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A time-domain analog weighted-sum calculation model is proposed based on an integrate-and-fire-type spiking neuron model. The proposed calculation model is applied to multi-layer feedforward networks, in which weighted summations with positive and negative weights are separately performed in each layer and summation results are then fed into the next layers without their subtraction operation. We also propose very large-scale integrated (VLSI) circuits to implement the proposed model. Unlike the conventional analog voltage or current mode circuits, the time-domain analog circuits use transient operation in charging/discharging processes to capacitors. Since the circuits can be designed without operational amplifiers, they can operate with extremely low power consumption. However, they have to use very high resistance devices on the order of GΩ. We designed a proof-of-concept (PoC) CMOS VLSI chip to verify weighted-sum operation with the same weights and evaluated it by post-layout circuit simulation using 250-nm fabrication technology. High resistance operation was realized by using the subthreshold operation region of MOS transistors. Simulation results showed that energy efficiency for the weighted-sum calculation was 290 TOPS/W, more than one order of magnitude higher than that in state-of-the-art digital AI processors, even though the minimum width of interconnection used in the PoC chip was several times larger than that in such digital processors. If state-of-the-art VLSI technology is used to implement the proposed model, an energy efficiency of more than 1,000 TOPS/W will be possible. For practical applications, development of emerging analog memory devices such as ferroelectric-gate FETs is necessary.

show abstract

Section: Time-domain Weighted-sum Calculation With Different-signed Wmentioning

confidence: 93%

“…Therefore, in the PoC circuit, all MOSFETs have the same ON resistance with the same gate voltage. To realize different analog weights, it is necessary to use analog memory devices such as resistance-change memory [27,12], ferroelectric-gate FETs [17], and floating-gate flash memory [1].…”

Section: Circuits and Architectures For Tact-based Neural Networkmentioning

confidence: 99%

Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Wang

Tamukoh

Matsukawa

2016

Neural Information Processing

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“…In the rst approach, an articial neural network (ANN) is trained by supervised learning, e.g., the backpropagation (BP) algorithm, [14][15][16][17][18] to construct a hardware accelerator for DNNs. [19][20][21] The major issue for this approach is the non-linear weight update and the large variability of resistive switching devices. 20,22 On the other hand, brain-inspired spiking neural networks (SNNs) aim at replicating the brain structure and computation in hardware.…”

Section: -13mentioning

confidence: 99%

“…[19][20][21] The major issue for this approach is the non-linear weight update and the large variability of resistive switching devices. 20,22 On the other hand, brain-inspired spiking neural networks (SNNs) aim at replicating the brain structure and computation in hardware. Learning usually takes place via spike-timing dependent plasticity (STDP), [23][24][25][26][27] where synapses can update their weight according to the timing between spikes of the pre-synaptic neuron (PRE) and post-synaptic neuron (POST).…”

Section: -13mentioning

confidence: 99%

Computing of temporal information in spiking neural networks with ReRAM synapses

et al. 2019

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Resistive switching random-access memory (ReRAM) is a two-terminal device based on ion migration to induce resistance switching between a high resistance state (HRS) and a low resistance state (LRS). ReRAM is considered one of the most promising technologies for artificial synapses in brain-inspired neuromorphic computing systems.However, there is still a lack of general understanding about how to develop such a gestalt system to imitate and compete with the brain's functionality and efficiency.Spiking neural networks (SNNs) are well suited to describe the complex spatiotemporal processing inside the brain, where the energy efficiency of computation mostly relies on the spike carrying information about both space (which neuron fires) and time (when a neuron fires). This work addresses the methodology and implementation of a neuromorphic SNN system to compute the temporal information among neural spikes using ReRAM synapses capable of spike-timing dependent plasticity (STDP). The learning and recognition of spatiotemporal spike sequences are experimentally demonstrated. Our simulation study shows that it is possible to construct a multi-layer spatiotemporal computing network. Spatiotemporal computing also enables learning and detection of the trace of moving objects and mimicking of the hierarchy structure of the biological visual cortex adopting temporal-coding for fast recognition.

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“…Monolithic 3-dimensional integration of these nonvolatile memories with CMOS, demonstrated in [24,25], allows designers to hide the logic circuitry underneath multiple layers of synapses, reducing silicon cost and increasing synapse density [4]. Gradual resistance change of these devices has been utilized as a synapse for variety of algorithms [26][27][28][29][30][31][32][33]. These devices can implement variations of biological [18] learning rules within a single device, further suggesting their use for neuromorphic hardware.…”

mentioning

confidence: 99%

Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses

Eryilmaz

Neftci

Joshi

et al. 2016

IEEE Trans. Electron Devices

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NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning

Cited by 169 publications

References 7 publications

Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

Computing of temporal information in spiking neural networks with ReRAM synapses

Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses

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