Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Otiaba, Kenny C.; Bhatti, Raj; Ekere, N.N.; Mallik, Sabuj; Alam, Md. Mahbubul; Amalu, Emeka H.; Ekpu, Mathias

doi:10.1016/j.microrel.2012.01.015

Cited by 55 publications

(26 citation statements)

References 14 publications

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“…1). These reliability issues impact primarily the interconnections, such as the attachments which connect the dies to a substrate and form the cathode terminal, and bond wire interconnections (anode terminal) (Ramminger et al, 1998;Ciappa, 2002;Otiaba et al, 2012).…”

Section: Introductionmentioning

confidence: 99%

Three‐dimensional damage morphologies of thermomechanically deformed sintered nanosilver die attachments for power electronics modules

Agyakwa

Dai

et al. 2019

Journal of Microscopy

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Summary A time‐lapse study of thermomechanical fatigue damage has been undertaken using three‐dimensional X‐ray computer tomography. Morphologies were extracted from tomography data and integrated with data from microscopy modalities at different resolution levels. This enables contextualization of some of the fine‐scale properties which underpin the large‐scale damage observed via tomography. Lateral views of crack development are presented, which show networks analogous to mud‐cracks. Crack fronts which develop in the most porous regions within the sintered attachment layer travel across the boundary into the copper substrate. The propagation characteristics of these cracks within the substrate are analysed. Evidence is provided of heterogeneous densification within the sintered joint under power cycling, and this is shown to play a major role in driving the initiation and propagation of the cracks. Examination of the texture (differing levels of X‐ray absorption) of virtual cross‐sectional images reveals the origins of the nonuniformity of densification. Finally, cracks within the sintered joint are shown to have a negligible impact on the conduction pathway of the joint due to their aspect ratio and orientation with respect to the assembly. Lay Description This paper concerns the use of three‐dimensional (3D) X‐ray tomography, a nondestructive technique, to perform cradle‐to‐grave studies of sintered nanosilver die‐attachments under operation. Sintered nanosilver die‐attachments have been proposed as a more reliable and environmentally friendly alternative to solder alloy joints for emerging power electronics module designs. However, their degradation mechanisms are not as well understood. This same sample‐study is about observing how the fine‐scale structure of a sintered attachment evolves and degrades over time. Using 3D tomography affords otherwise infeasible perspectives, such as virtual cross‐sections in the lateral plane of the attachment. These perspectives provide qualitative information which elucidates the degradation mechanisms. They demonstrate, for example, that the structure of the sintered attachment densifies under operation, and a consequence of this is the formation of shrinkage cracks in the most porous regions, much like mud‐cracks. Other imaging techniques (metallographic etching and scanning electron microscopy) have been used in correlation with 3D renderings of these cracks to analyse their propagation and reveal their relationship both with the internal structure of the sintered attachment itself, and the structure of the substrate to which it is joined. It is shown that the cracks develop within the sintered attachment layer and eventually cross over into the substrate. A comparison of two sintered attachments with contrasting bulk porosities allows the effect of initial bond quality on crack development to be examined.

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Section: Introductionmentioning

confidence: 99%

Three‐dimensional damage morphologies of thermomechanically deformed sintered nanosilver die attachments for power electronics modules

Agyakwa

Dai

et al. 2019

Journal of Microscopy

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“…From the state of the art, solder voids effects depend mainly on their position [5], [9][10], their size [1], [5], [7][8][9][10] and their distribution [1], [5], [11] for a functional assembly and a given operating mode. In our framework, the void is supposed to be cylindrical form.…”

Section: Hypothesis For the Studymentioning

confidence: 99%

“…Unfortunately, voids prevent heat transfer to cooling system and lead to current redistribution which depends on the electro thermal characteristics of power device [4]. Consequently, local hot spots can be formed in the active device [5]. This local temperature rise is known at the main factor which affects the device performance and reliability [6].…”

Section: Introductionmentioning

confidence: 99%

Solder void position and size effects on electro thermal behaviour of MOSFET transistors in forward bias conditions

Tran

Dupont²,

Khatir³

2014

Microelectronics Reliability

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This research aims to enhance the understanding on position and size effects on the electro thermal behaviour of low voltage power MOSFET transistors in forward bias condition. The numerical simulations is based on a fractional design of experiments (DoE). The performance of a finite elements model is discussed by comparing thermal and electrical measurements to results of finite elements simulation on a module of free void and voiding solder. The void in the model is afterwards parameterized in position and size, according to the fractional DoE of the study. The combined functions issued from the parametric simulations the DoE show the main impact of void size on temperature of the device and on the surface temperature of the bonding wires. From the numerical viewpoint, the most impacting position of void depends highly on the void size. The redistribution of current density and temperature on MOSFET chip and bonding wires due to solder void is also observed. A future experimental study in respect to the same DoE, is expected in prospect, in order to fulfil the complementarity for this approach.

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“…For a given technology in power application, an empiric level of 5% is generally used [9][10]. In reality, the void criteria levels are much more complicated to determine because they vary with void characteristics such as geometry, position, distribution [11][12][13][14][15][16]. It becomes crucial to optimize void thresholding in taking into account the electrothermal couplings.…”

Section: Introductionmentioning

confidence: 99%

Electrothermal Evaluation of Single and Multiple Solder Void Effects on Low-Voltage Si MOSFET Behavior in Forward Bias Conditions

Tran¹,

Dupont

Khatir

2017

IEEE Trans. Compon., Packag. Manufact. Technol.

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Solder void thermal effects on power module performance and reliability were investigated long time ago. The final goal is to determine void acceptability criteria or to remove them. Our approach is not to offer a more efficient method for neglecting void formation, but to suggest a method for optimizing void thresholding from multiphysical viewpoint. The major achievement is in the complete combination of modeling, experiments and optimization for void effect evaluation purpose. Especially, it has been introduced for the first time a real new highly coupled and detailed 3D-FEM electrothermal model of lowvoltage silicon MOSFET and the bonding wires in steady state. For single void case, the simulation results highlight local void effects on thermal performance of MOSFET in void area. However, no significant consequence on electrical performance is observed. Besides, the model shows a high dependence between void effects and back side metallization parameters. Electrical and thermal measurements performed on various single void configurations of experimental MOSFET prototypes offer a good agreement with numerical results. The study is then expanded to multi-voids case. The criticality of multi-voids corresponds to that of the most critical single void if the voids are not coalesced. These results offer an idea for a more optimized void inspection method in production line.

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Numerical study on thermal impacts of different void patterns on performance of chip-scale packaged power device

Cited by 55 publications

References 14 publications

Three‐dimensional damage morphologies of thermomechanically deformed sintered nanosilver die attachments for power electronics modules

Three‐dimensional damage morphologies of thermomechanically deformed sintered nanosilver die attachments for power electronics modules

Solder void position and size effects on electro thermal behaviour of MOSFET transistors in forward bias conditions

Electrothermal Evaluation of Single and Multiple Solder Void Effects on Low-Voltage Si MOSFET Behavior in Forward Bias Conditions

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