Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis

Nguyen, Huy; Chattejee, A.

doi:10.1109/92.863621

Cited by 81 publications

(48 citation statements)

References 8 publications

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“…In [19], a greedy algorithm is used to determine a solution with a low total operation cost. A 28 percent average area saving is achieved on some controllers and elliptic filters.…”

Section: Cost-function-based Search Methodsmentioning

confidence: 99%

Some optimizations of hardware multiplication by constant matrices

Boullis

Tisserand

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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Abstract-This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.

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“…In [19], a greedy algorithm is used to determine a solution with a low total operation cost. A 28 percent average area saving is achieved on some controllers and elliptic filters.…”

Section: Cost-function-based Search Methodsmentioning

confidence: 99%

Some optimizations of hardware multiplication by constant matrices

Boullis

Tisserand

16th IEEE Symposium on Computer Arithmetic, 2003. Proceedings.

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“…Most of the earlier works for finding common subexpressions in systems involving constant multiplications were based on finding common digit patterns in the set of constants multiplying a single variable [1][2][3][4][5][6][7][8][9]. These methods are good enough for optimizing systems where only single variable optimizations are required, such as the transformed form of FIR digital filters.…”

Section: Introductionmentioning

confidence: 99%

“…Figure 4 shows an example of matrix splitting used in a linear system, used in [2]. This matrix splitting was combined with shift-and-add decomposition of constant multiplications and an algorithm to eliminate common subexpressions in [2]. The algorithm was based on bipartite matching, similar to [3], but was extended to find common subexpressions among shifted forms of the constants.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…For example, it cannot detect the common subexpression B101b etween the constants B0101^and B1010^. The works in [2,24,25] perform a greedy optimization procedure to minimize the area of linear digital systems using combination of techniques modifying the coefficient matrices and common subexpression elimination. The modification of the coefficients is based on the fact that the complexity of the multiplier is dependant on the value of the coefficient and transforms the linear system by splitting the constant matrices such that the overall area is reduced.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Algebraic Methods for Optimizing Constant Multiplications in Linear Systems

Hosangadi

Fallah

Kastner

2007

J VLSI Sign Process Syst Sign Im

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Abstract. Constant multiplications can be efficiently implemented in hardware by converting them into a sequence of nested additions and shift operations. They can be optimized further by finding common subexpressions among these operations. In this work, we present algebraic methods for eliminating common subexpressions. Algebraic techniques are established in multi-level logic synthesis for the minimization of the number of literals and hence gates to implement Boolean logic. In this work we use the concepts of two of these methods, namely rectangle covering and fast extract (FX) and adapt them to the problem of optimizing linear arithmetic expressions. The main advantage of using such methods is that we can optimize systems consisting of multiple variables, which is not possible using the conventional optimization techniques. Our optimizations are aimed at reducing the area and power consumption of the hardware, and experimental results show up to 30.3% improvement in the number of operations over conventional techniques. Synthesis and simulation results show up to 30% area reduction and up to 27% power reduction. We also modified our algorithm to perform delay aware optimization, where we perform common subexpression elimination such that the delay is not exceeded beyond a particular value.

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