Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

Wu, Yung-Chun; Su, Ping; Chang, C.S.; Hung, Min-Feng

doi:10.1109/led.2008.2005070

Cited by 17 publications

(13 citation statements)

References 12 publications

(4 reference statements)

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“…The voltage windows are degenerated by 200 mV after 10-k cycles. The retention characteristics of cell before and after stress are measured at 85°C [11] and shown in Fig. 13(b).…”

Section: Experiments Resultsmentioning

confidence: 99%

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

Yang

Zheng

Wang

et al. 2017

IEICE Electron. Express

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A complete single-poly 2k-bit EEPROM solution including memory cells and peripheral circuits is presented and embedded into a passive RFID tag using a 0.18-µm standard CMOS technology. A charge pump with a Diode-C all-pass network and peripheral circuits without static current are proposed to reduce power consumption. A three-transistor memory cell is adopted for CMOS-compatibility, low operation voltage, and low complexity of drivers. The proposed EERPOM occupies an active area of 0.21 mm 2 . The leakage current during read operation is 36 nA from 1-V supply, while the static current during write operation is 1.3 µA from 1.8-V supply.

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“…The voltage windows are degenerated by 200 mV after 10-k cycles. The retention characteristics of cell before and after stress are measured at 85°C [11] and shown in Fig. 13(b).…”

Section: Experiments Resultsmentioning

confidence: 99%

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

Yang

Zheng

Wang

et al. 2017

IEICE Electron. Express

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“…For BBHE operation, the device exhibited almost no data retention capacity. The Ω-gate structure has a higher P/E efficiency than the tri-gate structure because the four corners of the channel are all surrounded by the gate structure [13,14]. The Ω-gate structure contributes to the equal sharing of the electric field and reduces the probability of leakage in the floating-gate devices in the form of stress-induced leakage current, improving the reliability of the device.…”

Section: Resultsmentioning

confidence: 99%

“…In our previous works [13,14], NWs were introduced into twin poly-Si TFT NVM to increase P/E speed. However, reducing the P/E voltage while ensuring the reliability of this device remains a challenge.…”

Section: Introductionmentioning

confidence: 99%

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory

Yeh

Hung

et al. 2013

Nanoscale Res Lett

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This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

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“…5 A simple EEPEROM that uses planar twin poly-Si TFTs has been proposed for SOP and 3-D stacked high-density memory applications, 2 6 7 and it is compatible to current very large scale integration (VLSI) electronic system. In our previous work, 8 a structure of tri-gate NWs was introduced into planar twin poly-Si TFTs EEPEROM to enhance the programming and erasing efficiency. However, * Author to whom correspondence should be addressed.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Charge Trapping Layer

Hung

Wu²,

Chiang³

et al. 2011

j nanosci nanotechnol

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This study investigates the characteristics of the planar twin poly-Si thin film transistor (TFT) EEPROM that utilizes a nitride (Si3N4) charge trapping layer. A comparison is made of two devices with different gate dielectrics, one a 16 nm-thick oxide (SiO2) layer for O-structure and the other 5 nm/10 nm-thick oxide/nitride layers for O/N-structure. Incorporating a nitride charge trapping layer and reducing the tunneling oxide thickness enable the O/N-structure EEPROM to enhance the program/erase (P/E) efficiency. Additionally, EEPROM formed with the tri-gate nanowires (NWs) structure can further enhance P/E efficiency and a large memory window because of its high electric field across the tunneling oxide. Reliability results indicated that, since the nitride layer contains discrete traps, the memory window can be maintained 2.2 V after 10(4) P/E cycles. For retention, the memory window can be maintained 1.9 V, and 30% charge loss for ten years of data storage. This investigation indicates that its possibility in future system-on-panel (SOP) of thin-film transistor liquid crystal display (TFTLCD) and 3-D stacked high-density Flash memory applications.

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Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

Cited by 17 publications

References 12 publications

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

A single-poly EEPROM with low leakage charge pump and peripheral circuits for passive RFID tag in a standard CMOS technology

Fabrication, characterization and simulation of Ω-gate twin poly-Si FinFET nonvolatile memory

Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Charge Trapping Layer

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