Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier

Chanda, Manash; Banerjee, Somnath; Saha, Dipankar; Jain, Swapnil

doi:10.1109/imac4s.2013.6526516

Cited by 9 publications

(2 citation statements)

References 13 publications

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“…A 16 bit logarithmic signal processor has been implemented using clocked adiabatic logic in 0.35μm and 10 times less power consumption than conventional CMOS was achieved [5] . 2*2, 4*4 and 8*8 vedic multipliers have been implemented using EEAL(Energy Efficient Adiabatic Logic) and the researchers achieved power saving of 64.3%, 56% and 41% respectively in 0.18μm CADENCE [6] . Adiabatic logic has been implemented in 8*8 tree multiplier and yielded 33% less power compared to conventional CMOS [7] .…”

Section: State Of the Artmentioning

confidence: 99%

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Babu¹,

Sivakumar²

2018

J. Phys.: Conf. Ser.

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Low power circuits and designs are the need of the hour as they find applications in electronic components which have power efficient processing capabilities. High speed processors are power consuming and multipliers contribute to a maximum extent for this power consumption. Thus, to achieve low power designs, adiabatic logic is one of the noted technologies in this regard. Adiabatic logic can be implemented for different types of circuit designs and this paper concentrates on a survey of various multipliers and adders that can be modified into a low power multiplier using adiabatic logic.

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Section: State Of the Artmentioning

confidence: 99%

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Babu¹,

Sivakumar²

2018

J. Phys.: Conf. Ser.

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“…Hence, the proposed device-based digital logic circuits have been implemented and their DC performances are compared with the conventional JL MOSFETs. We then compare its performance in terms of speed and energy consumption with Junction-less Double Gate MOSFET and suggest it be preferable for low power [27][28][29][30][31] high-speed [32][33][34] operations in the subthreshold regime.…”

Section: Introductionmentioning

confidence: 99%

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Mukherjee,

Ghosh,

Debnath

et al. 2024

JICS

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In this research work, Hetero-structure Junction-less MOSFET having a Silicon-Germanium source and high-k inner corner spacer is proposed and investigated. In this article, we have shown that the introduction of a high-k dielectric material in the inner corner spacer and a low-k dielectric material in the rest of the spacer in the optimally designed device leads to a substantial reduction in parasitic capacitances, resulting in higher operating speed. It was also shown that proper doping in the drain-source underlaps regime, can improve the short channel performance (SCP) of the device by increasing the effective gate length. The optimally designed proposed device produces on current (ION) ~0.33 mA and off current (IOFF) ~ 5.55 fA along with ION/IOFF=6.08x1010, Subthreshold slope (SS)=59.6 mV/decade and drain induced barrier lowering (DIBL)=82.2 mV/V. This paper also highlights the performance improvement of the proposed device in terms of both speed and energy consumption, as compared to that of Junctionless Double Gate MOSFET when implemented as logic gates.

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Complementary Energy Path Adiabatic Logic-Based Adder Design in 32 Nm FinFET Technology

Pittala

Rani²

2018

Advances in Communication, Devices and Networking

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Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier

Cited by 9 publications

References 13 publications

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

A survey on multipliers, adders and adiabatic logic styles suitable for power reduction

Hetero-Structure Junctionless MOSFET with High-k Corner Spacer for High-Speed and Energy-Efficient Applications

Complementary Energy Path Adiabatic Logic-Based Adder Design in 32 Nm FinFET Technology

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