Novel technique for detecting the open fault using electroplating

How effective are failure analysis methods for the 65nm cmos technology node?

“…One obvious solution is to add intermediary pads to the test structures in order to, artificially, decrease the structure size while leaving the other characteristics of the test structure (metal density, number of vias) unchanged. The other way is to develop alternative failure analysis methods like non-biased Thermal Laser Stimulation (NB-TLS) also called Seebeck Effect Imaging (SEI) [2], Resistive Contrast Imaging (RCI) and E-beam [3] or like the very attractive electroplating solution presented in [4]. The current ranges for which the mentioned fault isolation methods can be applied are summarized in Figure 2.…”

“…Small voids at metal / via interface have been observed. One other solution to analyze low current devices could be to use the Electro-Plating Localization Method presented in [4]. This technique, which is based on Cu electroplating, allows forming a Cu layer on top of a sample.…”