Novel structure of low-distortion fully-differential doubly-terminated ladder Gm-C filters

Choogorn, Terdpun; Mahattanakul, Jirayuth

doi:10.1109/ecticon.2011.5947783

Cited by 3 publications

(1 citation statement)

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“…Another topological transformation technique based on a transconductor input rearrangement not affecting the transfer function of G m -C filters was proposed in [29] and employed in [30][31][32][33]. Figure 2 shows the fundamentals of this idea.…”

Section: Introductionmentioning

confidence: 99%

Balanced G_m‐C filters with improved linearity and power efficiency

Algueta-Miguel

Blas

Lopez-Martin

2014

Circuit Theory & Apps

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A novel G m -C filter design technique is presented. It is based on floating-gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G m -C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all-pole G m -C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low-power second-order Butterworth G m -C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5-μm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. open-loop operation and the use of simpler topologies. However, these benefits come with the difficulty of achieving high linearity [4].Besides, the growing density of integration in CMOS technologies is reducing the thickness of the gate oxide of transistors, so supply voltages are also decreasing for reliability reasons: Voltages of 0.9 V are employed in modern technologies such as 90 nm and 65 nm, and the tendency is to keep decreasing. Furthermore, the growing proliferation of wireless and portable devices is leading to an intensive research on low-power integrated circuits for extending the lifetime of batteries.Thus, two challenging tasks are associated to G m -C filter design: linearity improvement to satisfy the modern communication standards and adaptation to the current low-voltage low-power requirements. Aimed to these goals, a novel G m -C filter design technique based on floating-gate MOS (FGMOS) transistors is proposed in this paper. It consists in a topological rearrangement of conventional filters without modifying the transconductor implementation and allows improving the filter linearity and relaxing the trade-off between the power consumption and the input range of the operational transconductance amplifier (OTA).The paper is organized as follows. In Section 2, an overview of several G m -C filter design methods available in the technical literature is presented. In Section 3, the fundamentals of the proposed FGMOS technique are explained, and considerations for applying it to G m -C filter design are discussed. The second-order effects of the presented method are studied in Section 4. In Section 5, a conventional second-order Butterworth G m -C filter is compared with its equivalent implementation obtained using the proposed design technique. Finally, conclusions are drawn in Section 6. All the proposed circuits have been fabrica...

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