Novel square root algorithm and its FPGA implementation

Kachhwal, Puneet; Rout, Bikash Chandra

doi:10.1109/icspct.2014.6884970

Cited by 15 publications

(4 citation statements)

References 3 publications

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“…Our motivation behind designing the MAD-NCC layer is basically to avoid vector-based square-root operations that exist in standard deviation calculation (Equation 4). Although there are novel approaches to square root calculation on FPGA [36], this operation is relatively slow compared to many other operations, such as division by 2 n (i.e. bit shift).…”

Section: Mad-ncc Layer Implementationmentioning

confidence: 99%

Filter design for small target detection on infrared imagery using normalized-cross-correlation layer

Demir¹,

Akagündüz²

2020

Turk J Elec Eng & Comp Sci

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In this paper, we introduce a machine learning approach to the problem of infrared small target detection filter design. For this purpose, similar to a convolutional layer of a neural network, the normalized-cross-correlational (NCC) layer, which we utilize for designing a target detection/recognition filter bank, is proposed. By employing the NCC layer in a neural network structure, we introduce a framework, in which supervised training is used to calculate the optimal filter shape and the optimum number of filters required for a specific target detection/recognition task on infrared images. We also propose the mean-absolute-deviation NCC (MAD-NCC) layer, an efficient implementation of the proposed NCC layer, designed especially for FPGA systems, in which square root operations are avoided for real-time computation. As a case study we work on dim-target detection on midwave infrared imagery and obtain the filters that can discriminate a dim target from various types of background clutter, specific to our operational concept.

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Section: Mad-ncc Layer Implementationmentioning

confidence: 99%

Filter design for small target detection on infrared imagery using normalized-cross-correlation layer

Demir¹,

Akagündüz²

2020

Turk J Elec Eng & Comp Sci

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“…Thus, at the end of the study, a complex circuit was simplified, occupying less space and became simpler. [11]. Zhou and Hu scaled the similar square root operation to a value between 0-1 after obtaining a 16-bit integer output value against 16-bit integer input.…”

Section: Introductionmentioning

confidence: 99%

Exponential Computing Digital Circuit Design Developed for FPGA-based Embedded Systems

Dereli¹,

Uç²

2020

acperpro

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Digital systems consist of thousands of digital circuit blocks operating in the background, working in their simplest form such as addition, subtraction, multiplication, division. In exponential expressions like square roots and cube roots, just like these circuits, it is found in many digital systems and performs tasks. Although these processes seem to be used only in circuits carrying out mathematical operations, they actually take an active role in solving many engineering problems. In this study, a digital circuit design that computes both the integer and a floating point exponent of a 32-bit floating-point number has been realized. This digital circuit, which is coded with VHDL language, can be used from beginner to advanced level in FPGA based systems. This digital circuit, which is coded with VHDL language, can be used from beginner to advanced level in FPGA based systems. In addition, three floating IP cores - logarithm, multiplication and exponent - were used in this digital circuit, and results were obtained with a total of five finite state machines in sixty-six clock pulse time.

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“…Other square‐root algorithms have been presented and implemented on reconfigurable logic devices. Kachhwal and Rout [5] presented an algorithm that uses a non‐standard, sub‐single precision 24‐bit floating‐point input, and returned a 16‐bit floating‐point output. The algorithm uses a so‐called Dwandwa Yoga method to determine the square‐root of the input.…”

Section: Introductionmentioning

confidence: 99%

Efficient digital implementation of a multi‐precision square‐root algorithm

Beasley

Watson

Clarke

2018

IET Computers & Digital Techniques

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In high performance computing systems and signal processing, there is a basic set of mathematical functions that are essential. While addition, subtraction and multiplication are well understood, there is less literature on square-rooting, which is a particularly time-and resource-consuming function. Traditional non-restoring algorithms produce a mantissa half the length of the input mantissa, causing a loss of precision. This study presents a method for increasing the accuracy of this algorithm. It is shown to work for all IEEE-754R standard floating-point numbers. Error analysis shows a 57-fold (for half-precision) and 134e6fold improvement (for double-precision) in the normalised error, equivalent to at most 1 Units of Least Precision. Resource and performance optimised variants are analysed and their throughput analysed. On an Intel Stratix V device, performance optimised implementations achieve a throughput of 717 MFLOPs. Resource optimised implementations on a low-cost device require only 127 Adaptive Logic Modules and 232 registers, with a throughput of 8.56 MFLOPs. All implementations are DSP block and memory free, saving valuable resources. The maximum throughput of the presented design is 15.5 times greater than that proposed by Pimentel et al. and two orders of magnitude greater than typical multiply-accumulate methods.

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Novel square root algorithm and its FPGA implementation

Cited by 15 publications

References 3 publications

Filter design for small target detection on infrared imagery using normalized-cross-correlation layer

Filter design for small target detection on infrared imagery using normalized-cross-correlation layer

Exponential Computing Digital Circuit Design Developed for FPGA-based Embedded Systems

Efficient digital implementation of a multi‐precision square‐root algorithm

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