Novel Probabilistic Combinational Equivalence Checking

Wu, Shih-chieh; Wang, Chun-Yao; Chen, Yung-Chih

doi:10.1109/tvlsi.2008.917397

Cited by 4 publications

(1 citation statement)

References 31 publications

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“…The formal verification methods are often divided into the three categories of theorem proving, model checking, and equivalence checking [1,2]. The equivalence checking involves the checking if the implementation of a circuit design is functionally equivalent to an earlier version which is described at the same level of abstraction, or at a specification described at a higher level of abstraction [3].…”

Section: Introductionmentioning

confidence: 99%

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

Pan

Ling

2010

AMM

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The formal verification is able to check whether the implementation of a circuit design is functionally equivalent to an earlier version described at the same level of abstraction, it can show the correctness of a circuit design. A new circuit verification method based on cone-oriented circuit partitioning and decision diagrams is presented in this paper. First of all, the structure level of every signal line in a circuit is computed. Secondly, the circuit is partitioned into a lot of cone structures. The multiple-valued decision diagram corresponding to every cone structure is generated. The verification procedure is to compare the equivalence of the multiple-valued decision diagrams of two types of cone structures. Experimental results on a lot of benchmark circuits show the method presented in this paper can effectively perform the equivalence checking of circuits.

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Section: Introductionmentioning

confidence: 99%

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

Pan

Ling

2010

AMM

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Pattern generation for Mutation Analysis using Genetic Algorithms

Yang

Wang

Huang

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Mutation Analysis (MA) is a fault-based simulation technique that is used to measure the quality of testbenches for mutant detections where mutants are simple syntactical changes in the designs. A mutant is said living if its error effect cannot be observed at the primary outputs. Previous works mainly focused on the cost reduction in the process of MA, because the MA is a computation intensive process in the commercial tool. For the living mutants, to the best of our knowledge, the commercial tool has not addressed the pattern generation issue yet. Thus, this paper presents a Genetic Algorithm to generate patterns for detecting living mutants such that the quality of the verification environment is improved. The experimental results show that more living mutants can be detected after adding the generated patterns in the testbench.

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Error Injection & Correction: An efficient formal logic restructuring algorithm

Huang

Lee

Lin

et al. 2012

2012 International SoC Design Conference (ISOCC)

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Novel Probabilistic Combinational Equivalence Checking

Cited by 4 publications

References 31 publications

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

Pattern generation for Mutation Analysis using Genetic Algorithms

Error Injection & Correction: An efficient formal logic restructuring algorithm

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Novel Probabilistic Combinational Equivalence Checking

Cited by 4 publications

References 31 publications

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

A New Verification Method of Digital Circuits Based on Cone-Oriented Partitioning and Decision Diagrams

Pattern generation for Mutation Analysis using Genetic Algorithms

Error Injection &amp; Correction: An efficient formal logic restructuring algorithm

Contact Info

Product

Resources

About

Error Injection & Correction: An efficient formal logic restructuring algorithm