Novel phase difference control technique of fractional-N PLL synthesizers by shifting the LE signals synchronized with a reference signal

Kitsukawa, Yusuke; Nakamizo, Hideyuki; Kihira, Kazunari; Mizutani, Hiroyuki; Tajima, Kazuo; Kawakami, Kenji

doi:10.1109/eumc.2014.6986792

Cited by 1 publication

(3 citation statements)

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“…[24] changes the MASH structure of SDM so that the controllable delay can be generated at the output of SDM. In [25], the output phase of fractional-N PLL is changed by shifting the load enable signal which controls the control data of the frequency divider. Both [24] and [25] achieve linear control of the output phase of PLLs in the range from 0°to 360°.…”

Section: Introductionmentioning

confidence: 99%

“…In [25], the output phase of fractional-N PLL is changed by shifting the load enable signal which controls the control data of the frequency divider. Both [24] and [25] achieve linear control of the output phase of PLLs in the range from 0°to 360°. However, in [24] and [25], the moment of phase synchronization can not be determined because there is no synchronization signal in different chips, and the phase adjustment amount of PLL in each chip needs to be manually configured.…”

Section: Introductionmentioning

confidence: 99%

“…Both [24] and [25] achieve linear control of the output phase of PLLs in the range from 0°to 360°. However, in [24] and [25], the moment of phase synchronization can not be determined because there is no synchronization signal in different chips, and the phase adjustment amount of PLL in each chip needs to be manually configured. A reference SDM is added to PLL in [26], which compensates the delay caused by cycle slip of SDM output codewords between different PLLs.…”

Section: Introductionmentioning

confidence: 99%

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Multi-chip phase synchronization circuit of fractional-N PLL

Yang¹,

Wang²,

Liu³

et al. 2023

IEICE Electron. Express

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A digital integrated circuit to realize multi-chip phase synchronization of fractional-N PLL with local oscillator divider is designed. An offset of fractional frequency ratio is added in phase difference calculation, which effectively avoids the large calculation error under some special fractional frequency ratios. Different from traditional one-time synchronization, a synchronization method with tracking mode is proposed, which can further reduce the phase error. The test result of the chip finished in 65nm COMS shows that the method of tracking mode and adding the fractional frequency ratio's offset are effective to reduce the error of phase synchronization to about 0.2°.

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