Novel Microwave Negative Capacitance. Application to a Wide-Range Tunable Capacitance

Kolev, S.; Delacressonnière, Bruno; Gautier, Jean-Luc

doi:10.1109/euma.2000.338651

Cited by 6 publications

(3 citation statements)

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“…Since the best location is near the ground plane, a grounded NIC topology will be easy to implement. In this sense, a grounded NII topology, first proposed by Kolev [10] has been selected. The circuit consists of two BF998 MOSFETs connected in the way shown in Fig.…”

Section: Design Examplementioning

confidence: 99%

“…These components do not obey the Foster theorem [7] and can compensate the reactance of the antenna by implementing a decrease of its reactance with the frequency allowing to match the antenna along broader bandwidths [8]. These non-Foster F. Albarracín-Vargas, F.J. Herraíz-Martinez and D. Segovia-Vargas are with the Department of Signal Theory and Communications, Carlos III University of Madrid (UC3M), 29811 Leganés, Madrid, Spain (e-mail: falbarracin@tsc.uc3m.es, dani@tsc.uc3m.es).. V. Gonzalez-Posadas is with elements, namely negative capacitors, and inductors, are realized by using 2-port active circuits so-called Negative Impedance Convertors (NICs) [9] or Negative Impedance Inverters (NIIs) [10]. A NIC is a 2-port active circuit, in which one port presents a negated (and possibly inverted) version of the impedance loading the other port.…”

Section: Introductionmentioning

confidence: 99%

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Design Method for Actively Matched Antennas With Non-Foster Elements

Albarracin-Vargas

González-Posadas

Herráiz-Martínez

et al. 2016

IEEE Trans. Antennas Propagat.

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The design of electrically small antennas loaded with active non-Foster elements is a topic whose interest has grown in the last years. In this paper, a new strategy for the design of actively matched antennas loaded with non-Foster elements is presented. The analysis of different parameters, such as the sensitivity to non-Foster circuit placement, the overall antenna system stability and current distributions, has to be considered in order to enhance the antenna performance. A design example using an electrically small antenna (ESA) and its realization is presented to validate the proposed strategy.

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Section: Design Examplementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design Method for Actively Matched Antennas With Non-Foster Elements

Albarracin-Vargas

González-Posadas

Herráiz-Martínez

et al. 2016

IEEE Trans. Antennas Propagat.

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“…The CMOS NIC principles introduced in [3] are applied in microwave frequencies up to 2 GHz using GaAS MMIC technology to produce negative resistance to compensate resonator losses of microwave resonator filters [6]. Negative capacitance realisation with 0,25 μm pHEMT process technology is first proposed by Kolev et al [7]. Negative inductance circuit which is separated from bias network using BiCMOS process is introduced in [8].…”

Section: Introductionmentioning

confidence: 99%

CMOS non-Foster Circuit Design Using 0.35μm BiCMOS Models by Cancelling the Parasitic Capacitances

Durukan¹,

Palamutcuogullari²

2022

World Congress on Electrical Engineering and Computer Systems and Science

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In this paper, an improved type of CMOS non-Foster circuit with the cross-coupled pair is proposed to produce negative resistance, negative capacitance and negative inductance in the frequency range between 100 MHz and 3 GHz. Non-Foster circuits are also called negative impedance converter (NIC) circuits. The proposed NIC circuit is designed to eliminate the gate-source parasitic capacitances of NMOS transistors which are the core elements of this cross-coupled topology with the help of on-chip inductors. The negative impedance conversion capability of the NIC circuit is shown analytically with the detailed mathematical formulations and proofs. The circuit is also simulated and verified in AWR Design Environment using 0.35µm BiCMOS transistor models comparatively for two cases with and without LC tank sub-circuit. The circuit is tested and verified with the loads of 50Ω resistance, 5 pF capacitance and 10 nH inductance to be converted negatively. The improvement in the negative impedance conversion rate of the NIC circuit is presented clearly with the impedance-frequency curves. The results show that the performance of the proposed NIC circuit is satisfactory with the help of gate-source parasitic cancellation. Additionally, the preliminary on-chip IC component placement of the NIC circuit using 0.35µm BiCMOS models is proposed for the realization and production.

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