Novel memristive logic architectures

Yang, Xin; Adeyemo, Adedotun; Bala, A.; Jabir, Abusaleh

doi:10.1109/patmos.2016.7833687

Cited by 6 publications

(9 citation statements)

References 14 publications

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“…7, especially, when the logic inputs are at the switching stages. In [20], [21], we proposed the purely memristive XOR architecture which consists of four memristors M 1 , M 2 , M 3 and M 4 as shown in Fig. 6(a).…”

Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

“…However, by connecting the PMOS transistor (PMOST) to the voltages V L1 and V L2 , the memristive XNOR operation can be realised in Fig. 6(c) [20], [21]. The output of the 1T-4M XOR architecture is demonstrated in Fig.…”

Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

“…The parasitic effects of the generic memristor model on the memristive logic architecture are demonstrated in Section III. With the help of the cascaded XOR structure, Section IV shows that our proposed memristive logic architectures [20], [21] provide more reliable performance as compared to the existing memristive logic technique [18]. The paper is concluded in Section V.…”

Section: Introductionmentioning

confidence: 99%

“…Since then, a number of memristor models have been proposed rapidly [2]- [9] with their own attributes (e.g. symmetricity and operating frequency) and have been applied in different areas such as high density memory design [10], [11], neuromorphic systems [12], [13] and logic design [14]- [21]. In the beginning, the proposed memristor models used for these applications did not consider the parasitic effects.…”

Section: Introductionmentioning

confidence: 99%

“…Then, [22]- [24] proposed a generic memristor model with parasitic components and it corresponds more closely to the memristive device in the real world. In this paper, we discuss how the parasitic components of the memristor model effect our proposed memristive logic architectures [20], [21]; and we also present the certain advantages of our proposed 3T-4M logic architecture over the existing 6T-2M logic architecture [18] while dealing with the cascaded XOR structure. For example, delay based Physical Unclonable Function (PUF) [25], [26].…”

Section: Introductionmentioning

confidence: 99%

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Parasitic effects on memristive logic architecture

Yang

Adeyemo

Bala

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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The most of the memristor based applications which have been proposed so far have not considered the parasitic components. In this paper, we apply a generic memristor model which includes the parasitic effects to our proposed memristive logic architectures. First, we show that the current response of the memristor has the decaying oscillation when the unit step function is applied. Then we demonstrated that our specific memristive logic structure can almost eliminate those effects which are generated by the parasitic components of the memristor. In addition, the propagation delay and the variation of the memristive XOR gate are increased because of the parasitic components. With the delay analysis on cascaded memristive logic design, the experimental results show that our 3T-4M memristive XOR architecture can build the more robust delay based memristive physical unclonable function (PUF) comparing to the existing memristive PUF.keywordsmemristor, hysteresis loop, memristive Logic gate, AND, OR, 3T-4M XOR, parasitic effects, physical unclonable function (PUF).

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Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%

Section: B Parasitic Effects On Memristive Xor Logic Architecturementioning

confidence: 99%