Novel low voltage current-mirror sense amplifier based Flip-Flop with reduced delay time

High resolution Frequency-based Delta-Sigma Modulator utilizing multi-phase quantizer

“…CMSA-FF is the fastest circuit with [8] the smallest delay value; t cq of the CMSA-FF is decreased by 48.9 % compared to Nikolics one [7] at VDD=300mV. In addition, the simulated results in [8] show that the setup/hold windows of the conventional SAFFs are far from the clock edge position, and the window in CMSA-FF is significantly reduced and closer to the clock edge position. This will help to solve the race problems and metastability in FDSM systems.…”

“…Timing performance of the CMSA-FF obtained from Spectre simulations were shown in paper [8] of the same authors. Fig.…”

“…Fig. 7 [8] compares the CLK→Q delay time (t cq ) of various FFs for typical MOS models at room temperature as the supply voltage VDD is scaled. CMSA-FF is the fastest circuit with [8] the smallest delay value; t cq of the CMSA-FF is decreased by 48.9 % compared to Nikolics one [7] at VDD=300mV.…”

“…7 [8] compares the CLK→Q delay time (t cq ) of various FFs for typical MOS models at room temperature as the supply voltage VDD is scaled. CMSA-FF is the fastest circuit with [8] the smallest delay value; t cq of the CMSA-FF is decreased by 48.9 % compared to Nikolics one [7] at VDD=300mV. In addition, the simulated results in [8] show that the setup/hold windows of the conventional SAFFs are far from the clock edge position, and the window in CMSA-FF is significantly reduced and closer to the clock edge position.…”

“…In the conventional sense amplifier FF (SAFF) [7], 4-stacked transistors from VDD to GND were used for charging and discharging operation, thus it will limit the speed of the FF. The better performance of the CMSAFF [8] can be achieved by reducing the number of stacked transistors. The speed improvement of the CMSA-FF is also obtained by reducing the discharging time and the setup time/hold time of the sense amplifier in the Pulse Generator stage as well as the delay of the Set-Reset (SR) Latch stage.…”