Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders

Park, Byeonggil; An, Seungyong; Park, Jongsun; Lee, Youngjoo

doi:10.1109/tcsii.2016.2596777

Cited by 11 publications

(7 citation statements)

References 9 publications

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“…Considering the broadcasting standards, we select two BCH codes over GF (2 16 ) and GF(2 14 ), where the number of correctable errors is equally set to 12. For fair comparisons, the area efficiency is used for this work, which is defined as follows [27]:…”

Section: Implementation Results Of Dual-m Sc and Cs Blocksmentioning

confidence: 99%

“…14 can be folded by sharing the greycolored processing elements (PEs), allowing more processing cycles [23]. Compared to this PE-level global folding, the recent architecture in [27] reveals that the multiplier-level local folding provides better area-efficiency by even reducing the internal critical delay as well as the hardware complexity. However, these techniques are only targeting the fixed-m KES architecture, no longer suitable for developing the areaefficient fully-flexible BCH decoder.…”

Section: A the Previous Folded-kes Architecturesmentioning

confidence: 99%

“…As the operating frequency of a whole BCH decoder is normally determined by the KES module [29], the decoding throughput can be degraded due to the increased clock period, even reducing the area efficiency of decoder. Based on the locally-folded multiplier architecture in [27], in this work, we present efficient architectures of processing cells (PCs) for supporting different field dimensions while enhancing the area efficiency remarkably.…”

Section: A the Previous Folded-kes Architecturesmentioning

confidence: 99%

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Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Park

Lee

2018

IEEE Access

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Recently, there are increasing demands for fully flexible Bose-Chaudhuri-Hocquenghem (BCH) decoders, which can support different dimensions of Galois fields (GF) operations. As the previous BCH decoders are mainly targeting the fixed GF operations, the conventional techniques are no longer suitable for multiple GF dimensions. For the area-optimized flexible BCH decoders, in this paper, we present several optimization schemes for reducing hardware costs of multi-dimensional GF operations. In the proposed optimizations, we first reformulate the matrix operations in syndrome calculation and Chien search for sharing more common sub-expressions between GF operations having different dimensions. The cellbased multi-m GF multiplier is newly introduced for the area-efficient flexible key-equation solver. As case studies, we design several prototype flexible BCH decoders for digital video broadcasting systems and NAND flash memory controllers managing different page sizes. The implementation results show that the proposed fully-flexible BCH decoder architecture remarkably enhances the area-efficiency compared with the conventional solutions.INDEX TERMS Bose-Chaudhuri-Hocquenghem (BCH) decoder, Galois-field (GF) arithmetic, optimization, low complexity, VLSI design.

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Section: Implementation Results Of Dual-m Sc and Cs Blocksmentioning

confidence: 99%

Section: A the Previous Folded-kes Architecturesmentioning

confidence: 99%

Section: A the Previous Folded-kes Architecturesmentioning

confidence: 99%

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Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Park

Lee

2018

IEEE Access

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“…The 18-parallel BCH decoder is utilized to decode a data block at every cycle. More precisely, as described in Figure 8b, the well-known three-stage pipelined decoder architecture associated with the codeword FIFO is introduced where each stage is fully optimized by adopting the previous techniques including the common subexpression (CSE)-elimination on syndrome calculation (SC) and Chien search (CS) units [34] and the low-complexity folded architecture on key equation solver (KES) unit [35]. As depicted in Figure 7, the decoded block is moved to the OFIFO, which is accessed by the serializer with the 16b output interface, providing the original media information to the wireless HMD.…”

Section: Hardware Architecture For Baseband Processingmentioning

confidence: 99%

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

et al. 2019

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This paper presents a novel baseband architecture that supports high-speed wireless VR solutions using 60 GHz RF circuits. Based on the experimental observations by our previous 60 GHz transceiver circuits, the efficient baseband architecture is proposed to enhance the quality of transmission. To achieve a zero-latency transmission, we define an (106,920, 95,040) interleaved-BCH error-correction code (ECC), which removes iterative processing steps in the previous LDPC ECC standardized for the near-field wireless communication. Introducing the block-level interleaving, the proposed baseband processing successfully scatters the existing burst errors to the small-sized component codes, and recovers up to 1080 consecutive bit errors in a data frame of 106,920 bits. To support the high-speed wireless VR system, we also design the massive-parallel BCH encoder and decoder, which is tightly connected to the block-level interleaver and de-interleaver. Including the high-speed analog interfaces for the external devices, the proposed baseband architecture is designed in 65 nm CMOS, supporting a data rate of up to 12.8 Gbps. Experimental results show that the proposed wireless VR solution can transfer up to 4 K high-resolution video streams without using time-consuming compression and decompression, successfully achieving a transfer latency of 1 ms.

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“…There have been many algorithms like Berlekamp–Massey (BM), Peterson, and others proposed to solve the key equation [3,7], but the inversion-less BM (iBM) algorithm is predominantly used in high throughput architectures [6,21]. Park et al [22] proposed a novel folded method to reduce the area in the hardware architecture, but the proposed method takes more clock cycles and is proportional to the folding factor. For the final step, the Chien Search (CS) algorithm is used to locate the error position from the error locator polynomial equation.…”

Section: Introductionmentioning

confidence: 99%

A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

Subbiah

Ogunfunmi

2019

Micromachines

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Bose–Chaudhuri–Hocquenghem (BCH) codes are broadly used to correct errors in flash memory systems and digital communications. These codes are cyclic block codes and have their arithmetic fixed over the splitting field of their generator polynomial. There are many solutions proposed using CPUs, hardware, and Graphical Processing Units (GPUs) for the BCH decoders. The performance of these BCH decoders is of ultimate importance for systems involving flash memory. However, it is essential to have a flexible solution to correct multiple bit errors over the different finite fields (GF(2 m )). In this paper, we propose a pragmatic approach to decode BCH codes over the different finite fields using hardware circuits and GPUs in tandem. We propose to employ hardware design for a modified syndrome generator and GPUs for a key-equation solver and an error corrector. Using the above partition, we have shown the ability to support multiple bit errors across different BCH block codes without compromising on the performance. Furthermore, the proposed method to generate modified syndrome has zero latency for scenarios where there are no errors. When there is an error detected, the GPUs are deployed to correct the errors using the iBM and Chien search algorithm. The results have shown that using the modified syndrome approach, we can support different multiple finite fields with high throughput.

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Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders

Cited by 11 publications

References 9 publications

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

High-Throughput and Low-Latency Digital Baseband Architecture for Energy-Efficient Wireless VR Systems

A Flexible Hybrid BCH Decoder for Modern NAND Flash Memories Using General Purpose Graphical Processing Units (GPGPUs)

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