Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing

Kumar, Shubham; Chatterjee, Swetaki; Dabhi, Chetan Kumar; Amrouch, Hussam; Chauhan, Yogesh Singh

doi:10.1109/iscas48785.2022.9937329

Cited by 8 publications

(4 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Each cell in the crossbar is a 1FeFET-1R structure. The ADC connected to the column is simulated using well-calibrated BSIM-IMG transistors based on measured data 28 . For all possible input and stored combinations, netlists for the column are generated using a Python script.…”

Section: Discussionmentioning

confidence: 99%

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

Soliman

Chatterjee

Laleni

et al. 2023

Preprint

Self Cite

View full text Add to dashboard Cite

Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level FeFET cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variabil21 ity effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based ferroelectric field-effect transistor (FeFET) devices. Unlike tradi23 tional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6%accuracy for handwriting recognition and 91.5%accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achiev28 ing 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional struc31 tural overhead.

show abstract

Section: Discussionmentioning

confidence: 99%

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

Soliman

Chatterjee

Laleni

et al. 2023

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…Each cell in the crossbar is a 1FeFET-1R structure. The ADC connected to the column is simulated using wellcalibrated BSIM-IMG transistors based on measured data 30 . For all possible input and stored combinations, netlists for the column are generated using a Python script.…”

Section: Simulation Methodologymentioning

confidence: 99%

First demonstration of in-memory computing crossbar using multi-level Cell FeFET

Soliman,

Chatterjee,

Laleni

et al. 2023

Nat Commun

Self Cite

View full text Add to dashboard Cite

Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level ferroelectric field-effect transistor (FeFET) cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variability effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based FeFET devices. Unlike traditional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6% accuracy for handwriting recognition and 91.5% accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achieving 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional structural overhead.

show abstract

“…2(b). The FDSOI transistor is also calibrated to the same 14 nm technology node using the BSIM-IMG model for different back-biases [39]. Finally, the parameters for the FE material, and other FE capacitor model parameters, are calibrated for both the FG and BG read to get an excellent match with TCAD data (see Fig.…”

Section: A Our Spice Modeling and Validation Of Fefetmentioning

confidence: 99%

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Kumar

Chatterjee

Thomann

et al. 2023

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory (NVM) technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with > 10 larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET.We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a crosslayer manner is indispensable.

show abstract

Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing

Cited by 8 publications

References 13 publications

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

First Demonstration of In-Memory Computing Crossbar using Multi-level Cell FeFET

First demonstration of in-memory computing crossbar using multi-level Cell FeFET

Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Contact Info

Product

Resources

About