Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips

Roy, Pranab; Patra, Mahua Raha; Rahaman, Hafizur; Dasgupta, Parthasarathi

doi:10.1109/idt.2013.6727133

Cited by 3 publications

(2 citation statements)

References 22 publications

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“…Since, the purpose that we need to fulfill requires a low power ADC with moderate resolution (~8-12 bits) and low sampling rate (~40kS/s), we believe SAR ADC is the most suitable choice. This paper proposes the design of a 8 bit low power SAR ADC with a double latch based clocked comparator to work in conjunction with the biochip block and the microfluidic droplet detection analyzer circuitry proposed in [9].…”

Section: Motivation Of This Workmentioning

confidence: 99%

“…A novel architecture has been proposed in [9] for processing and analysis of the optical detection results acquired at the detection site through successful biochip operation. One of the fundamental units of this proposed detection analyzer circuitry is the Analog to Digital Converter which works as a bridge between the biochip block and the digital post-processing unit.…”

Section: Motivation Of This Workmentioning

confidence: 99%

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A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications

Das

Sahoo

Roy

et al. 2014

18th International Symposium on VLSI Design and Test

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In recent years Digital Micro-fluidic Bio-chips have become a suitable choice for point of care diagnostics. These devices can detect various properties of human blood by means of an optical detection technique. The data acquisition is generally done using a LED-photodiode setup working in conjunction with the biochip. The voltage signal obtained at the photodiode output needs to be converted into digital data for further processing. A low power 8 bit SAR ADC is designed for this purpose and implemented in UMC 180 nm technology. The functionality testing of the ADC is done using Spectre simulator of Cadence Analog Design Environment. The ADC consumes about 45 μW of power at 13 pJ/conv-step from a 1.8 V supply at 40 kS/s and achieves a SNDR of 46.5 dB, ENOB of 7.4 bits at a signal bandwidth of 10 kHz. Mismatch analysis has been done by a set of Monte Carlo Simulations in Cadence. Even in worst case condition with 5% capacitance mismatch, the ADC achieves a SNDR of 43 dB, ENOB of 7 bits without any missing code.

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Section: Motivation Of This Workmentioning

confidence: 99%

Section: Motivation Of This Workmentioning

confidence: 99%