Novel Design Approach of Extended Gate-On-Source Based Charge-Plasma Vertical-Nanowire TFET: Proposal and Extensive Analysis

Kumar, Naveen; Raman, Ashish

doi:10.1109/tnano.2020.2993565

Cited by 28 publications

(16 citation statements)

References 24 publications

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“…The proposed nanowire device is grown vertically on the SOI (Silicon on Insulator) wafer [3]. In this device, intrinsic Si with 7nm thickness, is used for Drain (D), Source (S), Channel regions.…”

Section: Device Architecture and Simulation Parametersmentioning

confidence: 99%

“…SiO 2 makes up the oxide region surrounding the intrinsic silicon body in both devices. This use of SiO 2 facilitates the effortless process of deposition and feasibility of ultra-thin consistency settled above the surface of intrinsic silicon [3]. Channel length (L G ), Source length (L DS ) and Drain Length (L SD ) for the structure is 20 nm each.…”

Section: Device Architecture and Simulation Parametersmentioning

confidence: 99%

“…The Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which was rst invented in 1959 at Bell Labs, has been attempted to scale down for the past 50 years in order to attain high density, performance and cost-effectiveness [1]. However, Short channel effects (SCE) are introduced due to scaling down of MOSFET [2] which adds to the already existing limitation of threshold voltage (V TH ), high Off-state Current (I OFF ) and Sub-Threshold Swing (SS) (60 mV/dec) [3]. MOSFET-based nano-devices are more susceptible to SCE and it is di cult to attain Saturation of drain current due to the ballistic effect of charge carriers [4].…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, in this paper, a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor is being introduced which has a p-n-p-n con guration. Doping-less structure are more economical and defect-free [3]. There are two ways to induce doping in the intrinsic substrate which are Electrostatic and Charge Plasma (CP)Technique.…”

Section: Introductionmentioning

confidence: 99%

“…CP technique utilizes Electrodes having suitable work-function to induce pdoped Source and n-doped Drain regions [8]. Vertical Nanowire eases the device fabrication process compared to axial nanowires [3]. The cylindrical-shaped GAA structure offers stronger electrostatic control of the charge carriers due to greater surface inversion which in turn increases the drain current.…”

Section: Introductionmentioning

confidence: 99%

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Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

Lal

Verma

Kumar

et al. 2021

Silicon

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This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n con gured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (I OFF ) and threshold-voltage (V TH ) low and also improves the On-state current (I ON ) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of speci c work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n con gured structure, pocketing technique is used where the N+ heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two con gurations has been done, comparing various parameters like transconductance (G m ), output conductance (G D ), transfer characteristics (I D -V GS ), output characteristics (I D -V DS ), cut-off frequency (fT), total gate capacitance (C GG ) and intrinsic gain.

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Section: Device Architecture and Simulation Parametersmentioning

confidence: 99%

Section: Device Architecture and Simulation Parametersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

Lal

Verma

Kumar

et al. 2021

Silicon

Self Cite

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Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Madadi

Orouji

2022

Physica Status Solidi (a)

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This study describes a single‐gate silicon on insulator junctionless metal–oxide–semiconductor field‐effect transistor (SJL‐MOSFET) with inserted buried 4H‐SiC p‐type layer (B‐SJL‐MOSFET). The embedded p‐type layer is placed at the bottom of the active regions, achieving the full depletion of the channel in the off‐state mode. The p‐type layer affects the depletion region of the channel, which helps us have a full depletion area with a lower gate electrode work function. The main reason for using SiC material instead of silicon is the higher electrostatic integrity and a shorter natural length than silicon, resulting in a better short channel effect (SCE). In addition, the high‐k oxide is stacked for achieving lower natural length and better subthreshold swing (SS). The p‐type layer improves the leakage current (Ioff) by ≈105 in the event that it slightly diminishes the on‐state current (Ion) and improves the SS. Improvement of off‐current is due to higher barriers between source‐channel side and reduces the parasitic BJT in the off‐mode.

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Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments

Kumar,

Bhaskar,

Chotalia

et al. 2024

Microsyst Technol

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Novel Design Approach of Extended Gate-On-Source Based Charge-Plasma Vertical-Nanowire TFET: Proposal and Extensive Analysis

Cited by 28 publications

References 24 publications

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

Stacked Single‐Gate Silicon on Insulator 4H‐SiC Junctionless Field‐Effect Transistor with a Buried P‐Type 4H‐SiC Layer

Design, simulation and analog/RF performance evaluation of a hetero-stacked source dual metal T-shaped gate tunnel-FET in thermally variable environments

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