Novel CMOS and PTL Based Half Subtractor Designs

Rajput, Anju; Dua, Tripti; Kumawat, Renu; Srinivasulu, Avireni

doi:10.1109/ises52644.2021.00047

Cited by 5 publications

(3 citation statements)

References 14 publications

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“…From the simulations, it is observed that the proposed DCHA resulted in superior performance, because the CPHA utilizes the COPFA-based path forwarding properties. Table 8 compares the performance of the proposed DCHS with various state of art subtractors like PTLS [15], MTCMOSS [16], and TUTS [17]. From the simulations, it is observed that the proposed DCHS resulted in superior performance, because it performs subtraction using twos complement addition process.…”

Section: Resultsmentioning

confidence: 99%

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Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay-controlled hybrid adder (DCHA) and delay-controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay-controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR-ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology-based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.

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Section: Resultsmentioning

confidence: 99%

“…In [15], the authors developed the PTL-based subtractor (PTLS) with the gate-level modifications, which required less 2…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Florance

Prabhakar

Mishra

2022

Journal of Nanomaterials

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“…PTL uses the NMOS or PMOS to build the circuit. In this study, the NMOS is used in the circuit as the carrier mobility for N-type FET is found to be higher than the PMOS [9]. With the PTL approach, the Source of both NMOS is connected to the D0 and D1 respectively while the Drain of both NMOS is connected to F. The Gate of the upper FET is connected to S0' while the Gate of the bottom FET is connected to S0.…”

Section: Pass Transistor Logic 2:1 Mux Design Approachmentioning

confidence: 99%

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

Ying,

Johari

2023

J. Phys.: Conf. Ser.

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This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulation, it is found that the GDI approach used the least number of transistors followed by PTL and CMOS. The calculation of the propagation delay exhibits a substantial improvement of more than 95% using the GDI approach. The average power consumption shows a 55.30% and 35.16% reduction when compared to CMOS and PTL respectively. The PDP demonstrates an improvement of more than 95% when compared with conventional CMOS and PTL approaches. The same trend of observation is also achieved for EDP. The variation of the VDD and chirality has a markable effect on the propagation delay and average power consumption. This is a preliminary attempt to evaluate the performance of CNT implementation in MUX. The outcome can become the guideline for engineers working in circuit design using emerging materials for future nanoelectronics applications.

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Modified Low Power High Speed Approximate Adders For Energy Efficient Arithmetic Applications

Reddy¹,

Reddy²,

Kumar³

et al. 2023

2023 15th International Conference on Electronics, Computers and Artificial Intelligence (ECAI)

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Novel CMOS and PTL Based Half Subtractor Designs

Cited by 5 publications

References 14 publications

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Design and Implementation of ALU Using Graphene Nanoribbon Field‐Effect Transistor and Fin Field‐Effect Transistor

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

Modified Low Power High Speed Approximate Adders For Energy Efficient Arithmetic Applications

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