Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors

Veeramachaneni, Sreehari; Krishna, Midhun; Lingamneni, Avinash; Puppala, Saikumar; Srinivas, M.B.

doi:10.1109/vlsid.2007.116

Cited by 121 publications

(59 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The functionality of proposed 4-to-2 compressor cell is based on (9) -(13). (13) In the following, the proposed structure is discussed in detail. Fig.2. (a) CMOS design [10], (b) CMOS design [24], (c) CMOS design [22], (d) CMOS design [23], (e) CMOS design [12], ( f) CNFET design [25].…”

Section: Proposed 4-to-2 Compressor Cellmentioning

confidence: 99%

See 1 more Smart Citation

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

Darvishi¹,

Bagherizadeh²

2017

IJMECS

View full text Add to dashboard Cite

Abstract-In this paper, a new high-speed and energy efficient 4-to-2 compressor cell was presented using carbon nanotube field effect transistors (CNFETs). CNFET is very suitable for high-frequency and lowvoltage applications. In addition, in this paper several conventional and state-of-the-art 4-to-2 compressor cells are surveyed and compared. In order to evaluate the proposed designs, computer simulations are carried out using 32nm-CMOS and 32nm-CNFET technologies. Simulations are conducted using various low voltage power supplies, different temperatures, frequencies and load capacitors. Results of simulation demonstrate predominance of the proposed design in terms of power consumption, delay, and power-delay product (PDP) compared to other 4-to-2 compressor cells and they confirm that the proposed design is the fastest 4-to-2 compressor in various working circumstances.

show abstract

Section: Proposed 4-to-2 Compressor Cellmentioning

confidence: 99%

“…The efficiency of 4-to-2 compressor cells is exclusively influential on performance of multiplication computations [12]. A 4-to-2 compressor is functionally equal to two cascaded Full Adders (FAs) [9,13]. The structure of compressor could be of more interesting using the CNTFET technology.…”

Section: Introductionmentioning

confidence: 99%

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

Darvishi¹,

Bagherizadeh²

2017

IJMECS

View full text Add to dashboard Cite

show abstract

“…To reduce the delay of the partial product accumulation stage, 4-2 compressors have been widely employed nowadays for high speed multipliers. Because of their regular interconnection, these 4-2 compressors are ideal for the construction of regularly structured Wallace tree with low complexity [7]- [9]. Several 4-2 compressor circuits have been proposed for high-speed applications [3].…”

Section: Introductionmentioning

confidence: 99%

An Ultra High Speed Digital 4-2 Compressor in 65-nm CMOS

Aliparast¹,

Koozehkanani²,

Nazari³

2013

IJCTE

View full text Add to dashboard Cite

Abstract-The presented work deals an ultra high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. Current-mode techniques have been used to improve the overall performance of the compressor. New fully differential proposed circuit improves delay to less than 37% also reduces occupied area in comparison to other high-speed conventional compressor circuits. To evaluate the performance of the proposed circuit, conventional gate level structure has been chosen and all of the circuits have been simulated in 65-nm IBM CMOS process with 1.2V power supply voltage.Index Terms-Digital logic, 4-2 compressor, CMOS, high speed, current-mode. I. INTRODUCTIONWith ever-increasing possibilities that VLSI systems provide to realize high-speed digital building blocks, there is a trend toward using digital units to implement processing algorithms even for executing the tasks that were originally analog such as front-end communications. Microprocessors and digital signal processors rely on efficient implementation of fast arithmetic logic units to execute dedicated algorithms such as convolution and filtering [1], [2]. Adders and multipliers are most frequently and widely used arithmetic cells in realizing these processors. In most of these applications, multipliers dictate the overall performance of the system when speed and power consumption are considered as limiting factors. At the circuit design level, there is a great potential for optimization of these building blocks by voltage scaling or application of new CMOS logic styles for the implementation of its embraced combinational circuits [3]. A fast array or tree multiplier is typically composed of three subcircuits: 1) A Booth encoder for the generation of a reduced number of partial products. 2) A carry save structured accumulator for a further reduction of the partial products" matrix to only the addition of two operands. 3) A fast carry propagation adder (CPA) [4] carry representation. Among these subcircuits, the second stage of partial product accumulation, often referred to as the carry save adder (CSA) tree [5]- [7], contributes most to the overall delay and a high fraction of silicon area. Therefore, increasing the speed of CSA subcircuits is crucial to improve the performance of the multiplier. Early designs of CSA tree used the Dadda"s column compression technique [8] with the 3-2 counters, or equivalently the full adders to reduce the partial product matrix. To reduce the delay of the partial product accumulation stage, 4-2 compressors have been widely employed nowadays for high speed multipliers. Because of their regular interconnection, these 4-2 compressors are ideal for the construction of regularly structured Wallace tree with low complexity [7]-[9]. Several 4-2 compressor circuits have been proposed for high-speed applications [3]. In this paper, we begin with a brief introduction of conventional compressors which are composed of two full adders and each full adder optimized in gate level to achieve high spe...

show abstract

“…The lower order compressors such as 3 -2, 4 -2, 5 -2 were studied by many researchers (Dandapat et al, 2010) and (Veeramachaneni et al, 2007). In high speed multiplier, 4-2 compressors have been widely used to lower the latency of the partial product reduction stages.…”

Section: Introductionmentioning

confidence: 99%

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Marimuthu¹

2013

American Journal of Applied Sciences

View full text Add to dashboard Cite

This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V.

show abstract

Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors

Cited by 121 publications

References 6 publications

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

An Ultra High Speed Digital 4-2 Compressor in 65-nm CMOS

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Contact Info

Product

Resources

About