Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory

IEICE Electron. Express

Huang

et al. 2020

Self Cite

During manufacturing test, researchers usually overlook the importance of process variation defects and marginal defects, which can seriously affect test results of Early-Life-Failure (ELF). Theoretically, machine learning classification methods can be used to identify these two defects. In fact, when features overfitting or data distribution overlap seriously, classifiers perform poorly, it will not achieve the desired results. This paper first-ever proposes a kind of data preprocessing method combines improved K-Nearest Neighbors (KNN) regression classifier, so that the classification results will be enhanced in terms of classification performance. Experiment results demonstrate that the predictive accuracy is 45% higher than the traditional logistic regression method. This proposed method will drive critical new requirements for fault modeling, test generation and test application, and implementing them effectively will require a new level of collaboration between process and product developers.

Section: Introductionmentioning

confidence: 99%

Retraction:Reliability assurance in early-life-failure test through improved nearest neighbor regression

IEICE Electron. Express

Huang

et al. 2020

Self Cite

“…[3] and Ref. [2] shown that they have the same test escapes more or less as the proposed method. Nevertheless, there are more test time than proposed method, since they only consider the reduction of test escape but ignore the increase of test time.…”

Section: Comparison Of Other Test Flowmentioning

confidence: 65%

“…Traditionally, the test content, test order and test limits are fixed and only occasionally updated based on expert experience [2]. However, such experience is easy to make mistake and an automated alternative is desired.…”

Section: Introductionmentioning

confidence: 99%

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs

IEICE Electron. Express

Huang

et al. 2021

Self Cite

With the continuous drive toward integrated circuits (ICs) scaling, more test patterns are required in testing. However, the large number of patterns continues to increase test time and test costs. Thus, test costs of ICs are becoming more crucial yet more challenging. In this paper, we propose a novel adaptive test strategy to reduce test costs without increasing test escape, and using shortest path first (SPF) algorithm combined with K-Nearest Neighbor (KNN) to reorder the test patterns. The patterns which identify faults earlier are moved forward and applied first so as to save test time. In addition, the optimal test patterns are searched by means of a polynomial regression function and it provides a trade-off between test cost and test escape. Consequently, the optimization problem is converted into a mathematical function, in order to achieve broader applicability and generality. Experimental results demonstrate that the proposed method achieved 54.2 seconds time savings but leads to almost negligible test escapes increasing compared with traditional methods. The test pattern reordering method aims to find defects as early as possible. Furthermore, the proposed algorithm is completely software based and incurs no additional hardware overhead.

“…From Table 4 we can see the reorder-based [2] and [23] shown that the test time equivalent to test cost are less than the proposed method, but there are more test escapes than proposed method, they only consider the reduction of test cost and ignore the increase of test escape. The reorder-based Ref [7] and Ref [12] have the same test escape as proposed method, experimental results show that they only focus on test quality, but ignore the test cost. The most similar result is to based Ref [17] method, however, it is the reduction of test time and test escape by increasing a large amount of hardware circuit and area overhead, and the proposed method is completely software-based and does not require any additional hardware overhead.…”

Section: The Last Column Ofmentioning

confidence: 99%

“…From the abovementioned scientific issues, with the growing complexity of IC, testing needs more and more test patterns, the number of test patterns and individual test pattern length continue to increase as the size of IC gets larger, and thus, boosting test time and consequently test cost [12]. The objective of test is to cost effectively screen parts for high quality and reliability, while at the same time limiting unnecessary yield loss.…”

Section: Enormous Defect Detection Overlap Problem Between Test Typesmentioning

confidence: 99%

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

et al. 2020

IEEE Access

Self Cite

With the growing complexity of integrated circuits (IC), more and more test patterns are added to test set to test more defects, making the number of test pattern and individual test pattern length continues to increase as the size of IC gets larger, boosting test time and consequently test cost. To solve this problem, this paper proposes a kind of valid pattern identification method. The method uses machine learning to reorder the test pattern which can select the most effective patterns, to determine the optimal training set and test set first. Then, by means of the weighted SVMRANK algorithm to find the optimal pattern sequence. Experiment results demonstrate that the method only sacrifices 2% prediction accuracy in exchange for 3.89 times the time saving. The method aims at maximizing the accuracy of test, and minimizing the number of patterns. The proposed idea significantly improves the test time and test efficiency compared to conventional test flows. This is an innovative test cost reduction method with the growing complexity of IC. INDEX TERMS Adaptive test, machine learning, test reorder.