Novel 1T-dram with fin-gate and pillar structure for hole storage and data retention time improvement

Abstract

In this paper, we propose a novel SOl-based double-gate MOSFET with pillar structure for capacitorless one transistor dynamic random access memory (1 T-DRAM) application, which has fin-gate and .6ottom-Qate, and we name it as the FBG 1 T-DRAM. The proposed FBG 1 T-DRAM cell has an additional storage region, which can increase the holes storage. In terms of the memory performance, we obtained about 61.4 IlA1Ilm for the programming window and 204 ms for the data retention time. Furthermore, the device fabrication process has no self-aligned problems and is fully compatible with the conventional CMOS technology.

Raised Body Doping-Less 1T-DRAM With Source/Drain Schottky Contact

“…In Fig. 9, we compare the temperature-dependent performance of the proposed doping-less 1T-DRAM with other devices [4], [5], [21], [28], [29]. It can be see that our device has a stable programming window as the operating temperature is increased from 27 • C to 125 • C with a short gate length of 10 nm and drain biases.…”