Nouvelles architectures génériques de NoC

Zid, Mounir; Zitouni, Abdelkrim; Baganne, Adel; Tourki, Rached

doi:10.3166/tsi.28.101-133

Cited by 3 publications

(2 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other works are based on manual methods for modeling new architectures and topologies of NoC-based HDL [4][5][6]16].…”

Section: Related Workmentioning

confidence: 99%

“…A topology is considered as regular when all routers have the same degree, if not it is considered as irregular. For example, Spidergon from STMicroelectronics, GEXspidergon NoC [16] and Honeycomb [9] are considered as irregular. Spidergon [33] is one of the NoCs developed by STMicroelectronics and is being proposed as an evolution of the STNoC.…”

Section: Network-on-chip Characteristicsmentioning

confidence: 99%

See 1 more Smart Citation

System level modeling methodology of NoC design from UML-MARTE to VHDL

Elhaji

Boulet²,

Zitouni³

et al. 2012

Des Autom Embed Syst

Self Cite

View full text Add to dashboard Cite

The evolution of the semiconductor technology caters for the increase in the System-on-Chip (SoC) complexity. In particular, this complexity appears in the communication infrastructures like the Network-on-Chips (NoCs). However many complex SoCs are becoming increasingly hard to manage. In fact, the design space, which represents all the concepts that need to be explored during the SoC design, is becoming dramatically large and difficult to explore. In addition, the manipulation of SoCs at low levels, like the Register Transfer Level (RTL), is based on manual approaches. This has resulted in the increase of both time-to-market and the development costs. Thus, there is a need for developing some automated high level modeling environments for computer aided design in order to handle the design complexity and meet tight time-to-market requirements. The extension of the UML language called UML profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) allows the modeling of repetitive structures such as the NoC topologies which are based on specific concepts. This paper presents a new methodology for modeling concepts of NoC-based architectures, especially the modeling of topology of the interconnections with the help of the repetitive structure modeling (RSM) package of MARTE profile. This work deals with the ways of improving the effectiveness of the MARTE standard by clarifying and extending some notations in order to model complex NoC topologies. Our contribution includes a description of how these concepts may be mapped into VHDL. The generated code has been successfully evaluated and validated for several NoC topologies.

show abstract

“…Other works are based on manual methods for modeling new architectures and topologies of NoC-based HDL [4][5][6]16].…”

Section: Related Workmentioning

confidence: 99%

Section: Network-on-chip Characteristicsmentioning

confidence: 99%

System level modeling methodology of NoC design from UML-MARTE to VHDL

Elhaji

Boulet²,

Zitouni³

et al. 2012

Des Autom Embed Syst

Self Cite

View full text Add to dashboard Cite

show abstract

The Co-design of System-on-Chip in Africa: Spotlights on Industry, Research Efforts, Trends, and Challenges

Ammar¹,

Baklouti²,

Abid³

2014

Computing in Research and Development in Africa

View full text Add to dashboard Cite

An MDE approach for modeling network on chip topologies

Elhaji

Boulet

Meftali

et al. 2010

5th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era

View full text Add to dashboard Cite

International audienceNetwork on Chip (NoC) is a research field path that primarily addresses the global communication in System on Chip (SoC).The selected topology of the components interconnects plays a prime role in the performance of NoC architecture, for NoC conception, high-level synthesis approaches are utilized thus the behaviorally description of the system is refined into an accurate register-transfer-level (RTL) design for SoC implementation. In the recent MARTE (Modeling and Analysis of Real-time and Embedded Systems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topology. This paper presents a contribution for a new methodology for modeling NoC based Model Driven Architecture and the Modeling and Analysis of Real-Time and embedded System (MARTE), it aims to prove the effectiveness of standard MARTE in modeling irregular or globally irregular locally regular architectures. We will start this work by high level abstraction to reach low level through generated VHDL code

show abstract

Nouvelles architectures génériques de NoC

Cited by 3 publications

References 0 publications

System level modeling methodology of NoC design from UML-MARTE to VHDL

System level modeling methodology of NoC design from UML-MARTE to VHDL

The Co-design of System-on-Chip in Africa: Spotlights on Industry, Research Efforts, Trends, and Challenges

An MDE approach for modeling network on chip topologies

Contact Info

Product

Resources

About