Notice of Violation of IEEE Publication Principles: A 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]

Maxim, A.

doi:10.1109/cicc.2004.1358760

Cited by 6 publications

(9 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The circuit size in logic blocks is 1200 and the maximum operating frequency is around 80 [MHz]. Jitter of the proposed PLL for multiplication ratio 1 'Low-jitter PLLs' as in [4] and [5] aim to reduce jitters by themselves. Our approach solves the problem in case where these methods cannot attain.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A PLL configuration for reducing both incoming and inherent jitters

Kobayashi

Egashira

Kondoh³

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

View full text Add to dashboard Cite

In order to reduce jitters, both incoming and inherent, this article proposes a novel configuration. Feed-forward compensator improves jitter filtration, free from constraints on loop gain for reducing inherent jitters. Its effectiveness is verified on a prototype implemented on an FPGA, and experiments as a multiply-by-50 synthesizer result in 30-times reduction of inherent jitters and in halving of incoming jitters.

show abstract

Section: Introductionmentioning

confidence: 99%

“…Inherent jitter reduction is, on the other hand, relatively new [3][4][5]. Especially, frequency synthesizers with a large multiplication ratio are critical.…”

Section: Introductionmentioning

confidence: 99%

A PLL configuration for reducing both incoming and inherent jitters

Kobayashi

Egashira

Kondoh³

2009

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)

View full text Add to dashboard Cite

show abstract

“…However, charge pump bias voltage is provided by VCO. This may cause start-up or non-linear settling issues due to the additional feedback loop it includes [5]. Additionally, it does not use any VCO calibration methods that may degrade the noise performance of PLL.…”

Section: Introductionmentioning

confidence: 99%

A wide range adaptive bandwidth PLL with digital calibration

Yilmazer

Toker

2015

2015 International Symposium on Signals, Circuits and Systems (ISSCS)

View full text Add to dashboard Cite

This paper describes a new method for the design of wide range adaptive bandwidth PLLs. This method is implemented in two steps. In the first step named as coarse calibration, CCO (current controlled oscillator) center current is found using a digital frequency comparator. Voltage-to-current converters driving the CCO have a constant input voltage range. Additionally, their output current range is proportional to the CCO center current, so VCO gain tracks the center frequency. Charge pump current is also determined based on the update frequency in this step. In the second step named as fine tuning, CCO locks to the target frequency with a phase frequency detector (PFD) around the center current found in the first step. VCO gain tracking and finding the charge pump current based on the update frequency make the natural frequency proportional to the update frequency. Sample-reset loop filter provides a tracking mechanism between the update rate and the stabilizing zero. Furthermore, both the natural frequency and the stabilizing zero are made dependent on the ratio of circuit elements and bandgap reference voltages. This makes the loop dynamics less sensitive to process and temperature variations and virtually independent of output frequency and multiplication factor. The PLL has 500-2500MHz output frequency range and 1 to 50MHz update frequency range. The design was simulated in 0.18µm CMOS technology to verify the proposed method. Keywords-Phase locked loop, PLL, adaptive bandwidth, VCO calibration, sample-reset loop filters, frequency synthesizers I.978-1-4673-7488-0/15/$31.00 ©2015 IEEE

show abstract

“…In order to lower jitters, some approaches are proposed [6], [7]. However, jitter reduction is difficult in frequency synthesizers with a large multiplication ratio .…”

Section: Introductionmentioning

confidence: 99%

A low-jitter PLL for digital TV instrumentation

Kobayashi

Nakanishi

Kondoh³

2009

2009 IEEE International Symposium on Industrial Electronics

View full text Add to dashboard Cite

For consumer products of the digital age, 'stable' clock signals are crucial, leading to similar requirement for industrial instrumentation. In order to reduce jitters, rapid fluctuation in frequency, for such applications, this article proposes a novel configuration. Feed-forward compensator improves jitter fiitration, without sacrifice in the reduction of inherent jitters. Adaptive gain, which is set high for locking and low for jitter fiitration after locking, yields fast responses while keeping jitters low, as well. Its effectiveness is verified on a prototype implemented by an FPGA, and experiments as a muitiply-by-SO synthesizer result in 30-fold reduction for inherent jitters and no amplification of incoming jitters.

show abstract

Notice of Violation of IEEE Publication Principles: A 2-5GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter [frequency synthesizer application]

Cited by 6 publications

References 4 publications

A PLL configuration for reducing both incoming and inherent jitters

A PLL configuration for reducing both incoming and inherent jitters

A wide range adaptive bandwidth PLL with digital calibration

A low-jitter PLL for digital TV instrumentation

Contact Info

Product

Resources

About