Notice of Violation of IEEE Publication Principles: Design of efficient double tail comparator for low power

Chaudhari, Sharad S.; Pawar, Mahesh

doi:10.1109/iccsp.2015.7322829

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Sar Adc With Passive Adder1

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Cited by 8 publications

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“…4(b), respectively. It consists of capacitive DAC, double tail dynamic comparator [22,23] (Fig. 4(d)) and asynchronous SAR logic circuits.…”

Section: Sar Adc With Passive Addermentioning

confidence: 99%

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Pan

San

2019

IEICE Electron. Express

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A proof-of-concept delta sigma AD modulator using dynamic analog components with simplified operation mode is designed and fabricated in 90 nm CMOS technology. The measurement results of the experimental prototype demonstrate the feasibility of the proposed modulator architecture which can guarantee the reset time for ring-amplifier and relax the speed requirement on the asynchronous SAR quantizer. The peak SNDR of 77.93 dB and SNR of 84.16 dB are achieved while a sinusoid −4 dBFS input is sampled at 14 MS/s with signal bandwidth of 109 kHz. The total analog power consumption of the prototype modulator is 720 µW under the supply voltage of 1.2 V.

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“…4(b), respectively. It consists of capacitive DAC, double tail dynamic comparator [22,23] (Fig. 4(d)) and asynchronous SAR logic circuits.…”

Section: Sar Adc With Passive Addermentioning

confidence: 99%

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Pan

San

2019

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

Analysis of PMOS logic two tail comparator for less power consumption compared with CMOS comparator

Gajawada,

Mohana

2024

Fifth International Conference on Applied Sciences: Icas2023

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Design of Adiabatic Logic Two Tail Comparator for Low Power and Analyze with CMOS Comparator

Gajawada

Mohana

2022

2022 4th International Conference on Advances in Computing, Communication Control and Networking (ICAC3N)

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Notice of Violation of IEEE Publication Principles: Design of efficient double tail comparator for low power

Cited by 8 publications

References 6 publications

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Analysis of PMOS logic two tail comparator for less power consumption compared with CMOS comparator

Design of Adiabatic Logic Two Tail Comparator for Low Power and Analyze with CMOS Comparator

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