Notice of Violation of IEEE Publication Principles: Cost minimization for ASIC hybrid BIST designs

Abstract-By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents a multistage test strategy to be implemented on a BIST architecture for reducing test time of a simple core as solution for more global application of SoC testing strategy. This strategy implements its test pattern generation and output response analyzer in a BILBO architecture. The proposed method benefits from an irregular polynomial BILBO (IP-BILBO) structure to improve its test results. Experimental results on ISCAS-89 benchmark circuits show an average of 35% improvement in test time in proportion to pervious work.

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BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

Sadredini

Najafi

Navabi

2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

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Notice of Violation of IEEE Publication Principles: Cost minimization for ASIC hybrid BIST designs

Cited by 1 publication

References 6 publications

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

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