Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction

Abstract

Semiconductor design houses rely on third-party foundries to manufacture their integrated circuits (IC). While this trend allows them to tackle fabrication costs, it introduces security concerns as external (and potentially malicious) parties can access critical parts of the designs and steal or modify the Intellectual Property (IP). Embedded FPGA (eFPGA) redaction is a promising technique to protect critical IPs of an ASIC by redacting (i.e., removing) critical parts and mapping them onto a custom reconfigurable fabric. Only trusted parties will receive the correct bitstream to restore the redacted functionality. While previous studies imply that using an eFPGA is a sufficient condition to provide security against IP threats like reverseengineering, whether this truly holds for all eFPGA architectures is unclear, thus motivating the study in this paper. We examine the security of eFPGA fabrics generated by varying different FPGA design parameters. We characterize the power, performance, and area (PPA) characteristics and evaluate each fabric's resistance to SAT-based bitstream recovery. Our results encourage designers to work with custom eFPGA fabrics rather than off-the-shelf commercial FPGAs and reveals that only considering a redaction fabric's bitstream size is inadequate for gauging security.

Alice

“…This is the typical threat model for recent eFPGA redaction works [4,10]. In this scenario, the eFPGA security comes more from the fabric parameters and way the designer uses the fabrics rather than the specific redacted modules themselves [3,4]. We also assume the designers will use state-of-the-art eFPGA parameters from the security viewpoint [3].…”

“…The modules to be redacted will drive the customization of the eFPGA. Using open source frameworks offers additional degrees of freedom to the designer, where one can tune many parameters, as shown in [3]. This will allow the user to come up with architectures that are most suitable for the given design.…”

“…Recent studies on the security of FPGA redaction show that the resilience to SAT attacks is correlated more with the eFPGA fabric configuration and its utilization rather than the implemented module(s) [3,4,10]. For this reason, we focus more on the selection of the functionality to be redacted (together with its EDA implications), assuming the fabric configuration as given and "secure", and aiming at maximizing the fabric (both I/O and CLB) utilization.…”

“…Indeed, eFPGA implementations with poor I/O utilization are more prone to attacks because it is easier to identify stuck-at-0 outputs. Similarly, fabrics with low CLB utilization have less logic to be (successfully) recovered [3,4]. We then use a branch&bound algorithm to enumerate all possible eFPGA combinations that can be redacted together (lines 11-23) and obtain the full set of solutions.…”

High-level design methods for hardware security

“…Recent studies have shown that the security of eFPGA redaction is more related to the parameters of the eFPGA instance that is added to the design rather than the modules that are implemented on it [1,2]. However, the designers have to maximize the utilization of the reconfigurable logic and the I/O pins.…”