Nonvolatile static random access memory based on spin-transistor architecture

Abstract

The authors proposed and computationally analyzed nonvolatile static random access memory (NV-SRAM) architecture using a new type of spin transistor comprised of a metal-oxide-semiconductor field-effect transistor (MOSFET) and magnetic tunnel junction (MTJ) that is referred to as a pseudo-spin-MOSFET (PS-MOSFET). The PS-MOSFET is a circuit approach to reproduce the functions of spin transistors, based on recently progressed magnetoresistive random access memory technology. The proposed NV-SRAM cell can be simply configured by connecting two PS-MOSFETs to the storage nodes of a standard SRAM cell.

Spin-dependent transport properties of a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor structure

“…4 In previous studies on spin MOSFETs, 5,6 the drain-source current was controlled by the gate-source voltage and magnetization configuration of the source and drain; however, the magnetoresistance (MR) ratios (0.1% 5 and 0.005% 6 ) were too small to be put into practical applications in these studies, and thus spin MOSFET with a high MR ratio is strongly required.…”

Devices and Applications: Spin Transistors and Spin Logic Devices

“…Note that there is a very different way for realizing spin transistors. The pseudo-spin-MOSFET [1,18] is a simple circuit for reproducing the functions of a spin-MOSFET using an ordinary MOSFET and an MTJ.…”

Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure

“…By utilizing a twostep MTJ configuration, the area of the NVPS using Ref. 15 becomes smaller than that of the previous one. However, there are wasted control transistors in terms of the NVPS.…”

“…However, a conventional MTJ-based NVPS tends to be large because the nonvolatile storage element requires large write-control transistors for supplying sufficient bi-directional write current through MTJ devices. 8,15 In this paper, a compact NVPS is fabricated using 90 nm CMOS technology together with perpendicular-MTJ (p-MTJ) devices. 13 Because routing information does not change frequently once it is programmed into an NVPS, high-speed read and write access is not required, which greatly simplifies the structure of the NVPS.…”