Nonvolatile low-voltage memory transistor based on SiO2 tunneling and HfO2 blocking layers with charge storage in Au nanocrystals

Abstract

We demonstrate a low voltage nonvolatile memory field effect transistor comprising thermal SiO2 tunneling and HfO2 blocking layers as the gate dielectric stack and Au nanocrystals as charge storage nodes. The structure exhibits a memory window of ∼2 V at an applied sweeping voltage of ±3 V which increases to 12.6 at ±12 V. Retention tests show an extrapolated loss of 16% after ten years in the hysteresis width of the threshold voltage. Dynamic program/erase operation reveal an approximately pulse width independent memory for pulse durations of 1 μs to 10 ms; longer pulses increase the memory window while for pulses shorter than 1 μs, the memory windows vanishes. The effective oxide thickness is below 10 nm with very low gate and drain leakage currents.

Applications of Nanotechnology in Next-Generation Nonvolatile Memories

“…However, since the early 2000s, the focus has turned toward the various metallic nanocrystals for their higher work function and higher density of states compared to semiconducting ones. Various metallic ncs like Ni [20][21][22], Ag [21,23,25], W [25,26], Pt [24,26], Au [22,24,27,28], and Ru [33] have been reported in recent literature. The higher work function of the metallic ncs make for deeper potential wells, and the higher density of states give them the capability of storing more electrons per nanocrystal, than semiconducting ncs [21][22][23][24][25][26][27][28][31][32][33][34].…”

“…Another point worth mentioning here is that the application of F-N tunneling to write/erase data in these type of devices results in a high F-N stress on the tunnel oxide structure, and therefore the write voltage/erase voltage is selected as the voltage at which the F-N currents just starts to dominate the DT current [26,27,31]. This is basically the "onset" voltage for F-N tunneling mechanism.…”

“…Now it is worth mentioning here that these devices are research purpose devices having considerably thicker dielectrics and Si substrates than industry standard flash. With scaling of the device dimensions and the use of high-k dielectric stacks, the write voltage usually lies in the range 5-7 V [20,27,34].…”

Improving the precision of Hall effect measurements using a single-crystal copper probe

“…Therefore, it is important to develop a grainfree, highly conductive material. 4,7,9 We previously reported that the conductivity of singlecrystal copper (SCC) was enhanced by 9% over oxygen-free copper (OFC) between 70 K and 300 K. 9 This resistivity reduction of 9% is due to the absence of GB scattering in the SCC material and translates to a nearly 100% reduction in distortion during signal transfer.…”

Bioorganic nanodots for non-volatile memory devices

“…Electronic mail: rgil@post.tau.ac.il memory media that contains discrete charge storage crystalline nano-dots (NDs). [14][15][16][17][18][19][20][21] The NDs layer should have high NDs surface density, nm-scaled structure, size and shape uniformity, and lateral isolation (i.e., electrically isolated NDs). As of now, Au or Pt nanocrystals are the most popular NDs for new-generation NVM.…”