Nonvolatile Charge-Trap Memory Transistors With Top-Gate Structure Using In–Ga–Zn-O Active Channel and ZnO Charge-Trap Layer

Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

“…Therefore, increasing the tunneling layer thickness was found to be desirable to obtain longer retention characteristics. Furthermore, the retention time was also improved after the introduction of a protection layer prepared on the ZnO CT layer, as compared to previous devices [13]. As a result, we observed a trade-off between program speed and memory retention characteristics when the tunneling layer thickness was varied in our proposed CTM-TFTs.…”

“…There are two points worth discussing regarding these results. First, the program speed typically improved compared to those of our previous devices [13,14]. For the fabrication of CT1 and CT2, the tunneling and blocking layer thicknesses increased and decreased to 10 and 50 nm, respectively.…”

“…As a result, offprogramming was successfully initiated, even with 10-ls program pulses for both devices. For our proposed CTM-TFTs, the program speed was mainly dominated by the off-program speed due to the fact that the on-programming was much faster than the off-programming because the roles of the primary electrons originated from the n-type ZnO semiconductor [13,14]. The second concern is related to the geometries between and relative sizes of the CT layer and active regions.…”

“…In addition, from our previous studies, it was determined that the read-out voltage condition during the retention period is very important for our proposed top-gate-structured CTM-TFTs due to the unexpected de-trap process, especially under higher read-out V DS conditions [13]. Therefore, careful attention is required when determining the V DS conditions for certain memory-embedded circuit applications in which a higher V DS bias is required for the proper operation of a designed integrated circuit.…”

“…Although many of the studies on CTM-TFTs that employ oxide semiconductor channels have focused on the CT materials, it is also important to investigate the detailed relationship between memory performance and device design [3,11,12]. We previously proposed and characterized CTM-TFTs with an all-oxide gate stack composed of Al 2 O 3 blocking/ZnO CT/Al 2 O 3 tunneling/In-Ga-Zn-O channel layers [13,14]. In the present work, we focused on two design parameters to improve the performance of CTM-TFTs: (1) the effects of variations in tunneling and CT layer thicknesses on memory behaviors were carefully investigated, and (2) the effects of variations in CT layer geometry on the disturbance characteristics were examined for embedded memory applications.…”