Nonvolatile and Robust Design of Content Addressable Memory Cell Using Magnetic Tunnel Junction at Nanoscale Regime

Dwivedi, Amit Krishna; Islam, Aminul

doi:10.1109/tmag.2015.2454477

Cited by 13 publications

(5 citation statements)

References 24 publications

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“…P dyn = P switch + P S.C + P glitch (5) The average power dissipation can be given in the (6) [23], [24], 2)-( 3)) in (4), the total power dissipation is summarized in the (7) [23], [24],…”

Section: Sources Of Power Dissipationmentioning

confidence: 99%

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Power optimization of binary division based on FPGA

Nasser

Hashim

2021

IJEECS

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In modern very large scale integrated (VLSI) digital systems, power consumption has become a critical concern of VLSI designers. As size shrinks and density increases in chips, it will be a challenge to design high performance and low-power digital systems. Therefore, VLSI designers are trying to reduce power dissipation in these systems by using power optimization techniques. Different mathematical operations can be found in the architectures of most digital systems. The focus of this paper is division. In comparison to other basic computational operations, division requires more iterations, takes a long time, covers a large area, and consumes more power from the digital system. As a result, the system's design requires high speed and a low-power divider in order to improve its overall performance. This paper focuses on dynamic power dissipation. In order to determine which design consumes the lowest dynamic power, different system designs of digit-recurrence division algorithms, such as restoring division and non-restoring division are suggested. An innovative power-optimization technique, the very hardware descriptions language (VHDL) technique, is utilized to the suggested system designs. The VHDL technique achieved the higher optimization in dynamic power, at 93.66% for non-restoring division with internal-loop iteration, than traditional approaches.

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“…P dyn = P switch + P S.C + P glitch (5) The average power dissipation can be given in the (6) [23], [24], 2)-( 3)) in (4), the total power dissipation is summarized in the (7) [23], [24],…”

Section: Sources Of Power Dissipationmentioning

confidence: 99%

“…Generally, the significant advantages of power optimization are increased system reliability, battery life efficiency, noise immunity, lower system cooling and packaging cost, and demand for portable systems [4]. The total power dissipated in a VLSI circuit is the sum of dynamic power and leakage or static power [5].…”

Section: Introductionmentioning

confidence: 99%

Power optimization of binary division based on FPGA

Nasser

Hashim

2021

IJEECS

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“…Low power circuits have been a topic of much interest due to its potential applications in the battery‐operated portable gadgets or wearable devices. Most of the recent works are focused towards the miniaturisation of circuits mainly by reducing the number of transistors in the design, hence the chip area and average power consumption of the circuit [1].…”

Section: Introductionmentioning

confidence: 99%

Variation resilient reliable design of trigger pulse generator

Kumar

Dwivedi

Islam

2020

IET Circuits, Devices & Systems

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“…With the rapid expansion of modern technologies, researchers have been motivated towards nonvolatile memory elements [1]. Nonvolatile elements such as spin transfer torque (STT) based magnetic tunnel junction (MTJ) and spin valve are promising candidates for nonvolatile Random Access Memory (MRAM) [2][3][4]. Nonvolatile memory elements are more reliable and convenient to be included in any circuit architecture with a prolonged data holding and retention capabilities as compared to the conventional volatile memory elements [3,5].…”

Section: Introductionmentioning

confidence: 99%

“…Nonvolatile elements such as spin transfer torque (STT) based magnetic tunnel junction (MTJ) and spin valve are promising candidates for nonvolatile Random Access Memory (MRAM) [2][3][4]. Nonvolatile memory elements are more reliable and convenient to be included in any circuit architecture with a prolonged data holding and retention capabilities as compared to the conventional volatile memory elements [3,5]. Phase change random access memory (PCRAM) has emerged as a promising candidate to replace the traditional memory circuits [6].…”

Section: Introductionmentioning

confidence: 99%

Investigating Phase Transform Behavior in Indium Selenide Based RAM and Its Validation as a Memory Element

Sourav

Dwivedi

Islam

2016

Journal of Materials

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Phase transform properties of Indium Selenide (In2Se3) based Random Access Memory (RAM) have been explored in this paper. Phase change random access memory (PCRAM) is an attractive solid-state nonvolatile memory that possesses potential to meet various current technology demands of memory design. Already reported PCRAM models are mainly based upon Germanium-Antimony-Tellurium (Ge2Sb2Te5 or GST) materials as their prime constituents. However, PCRAM using GST material lacks some important memory attributes required for memory elements such as larger resistance margin between the highly resistive amorphous and highly conductive crystalline states in phase change materials. This paper investigates various electrical and compositional properties of the Indium Selenide (In2Se3) material and also draws comparison with its counterpart mainly focusing on phase transform properties. To achieve this goal, a SPICE model of In2Se3 based PCRAM model has been reported in this work. The reported model has been also validated to act as a memory cell by associating it with a read/write circuit proposed in this work. Simulation results demonstrate impressive retentivity and low power consumption by requiring a set pulse of 208 μA for a duration of 100 μs to set the PCRAM in crystalline state. Similarly, a reset pulse of 11.7 μA for a duration of 20 ns can set the PCRAM in amorphous state. Modeling of In2Se3 based PCRAM has been done in Verilog-A and simulation results have been extensively verified using SPICE simulator.

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Nonvolatile and Robust Design of Content Addressable Memory Cell Using Magnetic Tunnel Junction at Nanoscale Regime

Cited by 13 publications

References 24 publications

Power optimization of binary division based on FPGA

Power optimization of binary division based on FPGA

Variation resilient reliable design of trigger pulse generator

Investigating Phase Transform Behavior in Indium Selenide Based RAM and Its Validation as a Memory Element

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