Using a 67 GHz PSA, the phase noise at divide-by-2 frequency can be measured. The phase noise of the divide-by-2 frequency of 42.665 GHz, corresponding to the locked frequency of 85.33 GHz, was measured as shown in Figure 9. The phase noise of the L-band frequency reference is also overlapped on the same graph for comparison. Phase noise at 100 kHz and 1 MHz offset is 2100.1 and 2106.2 dBc/Hz, respectively, degrading about 30 dB from the reference noise floor. Six decibel further degradation could be expected for W-band locked frequencies. The phase noise performance is strongly limited by the reference noise floor.
CONCLUSIONA W-band FS is presented in this work, fabricated in a standard 65 nm CMOS process, which consists of a K-band SSPLL and a 34 W-band FM. The proposed architecture could lower the in-band phase noise from the charge pump by M 2 times compared to the conventional fundamental FS. The proposed FS dissipates a total power of 54 mW. The measured phase noise of divide-by-2 frequency is 2100.1 dBc/Hz at 100 kHz offset and 2106.2 dBc/Hz at 1 MHz offset, respectively. It covers 9.6% tuning range of 79 to 87 GHz. The total FS chip occupies about 1.48 3 0.8 mm 2 area with on-chip loop filter and pads. To the authors' knowledge, this work is the first CMOS W-band divider-less FS consisting of SSPLL and FM. REFERENCES 1. K. Nguyen, H. Kim, and C. Sodini, A 76 GHz PLL for mm-wave imaging applications, In: IEEE MTT-S International Microwave