Non-regression approach for the behavioral model generator in mixed-signal system verification

Efficient Circuit Structure Analysis for Automatic Behavioral Model Generation in Mixed-Signal System Simulation

“…Therefore, the model construction efforts can be greatly reduced without losing the generality for different circuits. In recent years, a structural macromodeling technique has been used to model the building block behaviors for analog circuits, because this hierarchical approach is able to deal with different fidelities and various sizes of circuits [19,20,27,28]. However, accurate structure recognition techniques are the key to enable this kind of modeling approach, which are introduced in next section.…”

“…However, building accurate yet efficient behavioral models for analog circuits is not an easy job due to their nonlinear properties. For specific circuits, such as PLL, ADC, DAC, etc., many approaches [25][26][27][28] are available to build these behavioral models automatically. In order to deal with different kinds of circuits, some automatic behavioral model generators are developed based on statistical approaches [26] or structure-based approaches [27,28].…”

“…For specific circuits, such as PLL, ADC, DAC, etc., many approaches [25][26][27][28] are available to build these behavioral models automatically. In order to deal with different kinds of circuits, some automatic behavioral model generators are developed based on statistical approaches [26] or structure-based approaches [27,28]. Although those previous works are able to extract the required behavioral models from the given netlist, several limitations still exist that prevent their being used in large AMS designs.…”

“…If the required behavioral models can be automatically generated from the given designs, this could be an attractive approach for designers. Because the behavioral models of analog circuits and digital circuits are built in different ways [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28], it is necessary to correctly identify different circuit blocks in the transistor-level netlist of the whole system. This can also help to understand the behavior of the flattened transistor-level netlists extracted from layouts in reverse engineering or commercial tools.…”