Non-quasi-static small-signal modeling and analytical parameter extraction of SOI FinFETs

Abstract

Accurate modeling and analytical parameter extraction of the non-quasi-static small-signal model of FinFETs are presented using a three-dimensional device simulator. Using simple -and -matrices calculations, the extrinsic gate-to-drain/source capacitance and source/drain resistance are de-embedded from the small-signal equivalent circuit. The analytical parameter extractions are performed by -parameter analysis after removing the extrinsic gate-to-drain/source capacitance and source/drain resistance. Accuracy of the model and extraction method is verified with the device-simulation data up to 700 GHz. Without any complex fitting and optimization steps, the total modeling rms error of the -parameter up to 700 GHz was calculated to be only 1.9 % in the saturation region and 2.1 % in the linear region. Also, the bias dependencies of the small-signal parameters are presented.

Physical Insights Into Electric Field Modulation in Dual-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula> Spacer Asymmetric Underlap FinFET

“…15(a), the variation in the ratio of the extrinsic drain-side parasitic fringing capacitance due to the dual-k spacer C fod [35] and total gate capacitance C gg for different values of k and t sp is presented. It is observed that for lower value of t sp , initially, the ratio (C fod /C gg ) increases and then decreases with k suggesting improvement in gate control, whereas, for higher value of t sp , the ratio monotonically increases with k suggesting gate control degradation due to the parasitic fringing capacitance.…”

“…The optimization of t sp is performed considering I ON of the device and the corresponding C fod . The C fod is extracted as described in [35]. In order to optimize t sp , initially, t sp = 10 nm is considered as the upper limit since beyond this value of t sp , the improvement in I ON is negligible, as shown in the inset of Fig.…”

Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions

“…An accurate Y-parameter analysis from the small signal equivalent circuit is carried out for the extraction of parasitic as well as the intrinsic components. The small signal equivalent circuit for high frequency analysis with the inclusion of the non-quasi static effects is taken from [12] as shown in Fig. 10 where the box represents the intrinsic components with R gs and R gd being the distributed channel resistances, g m and g ds are the transconductance and drain conductance and L sd is the inductance to include the effect of the time constant s m due to the non quasi static effects (NQSs).…”

“…As reported in [12], the [Y in ] matrix is converted to [Z in ] and source/ drain resistance R s and R d are de-embedded to obtain the pure intrinsic Y-parameter matrix [Y int ]. The channel resistance method was implemented for the extraction of source/drain series resistance with three different values of the overdrive voltage and a value of 10.785 X was obtained.…”

A broadband small‐signal model extraction methodology over 0.2‐220 GHz for bulk FinFETs in RF CMOS technology

“…According to the 2016 prediction of the ITRS 2.0 roadmap, FinFETs will continue to follow the scaling trend of CMOS transistors to the 5‐nm technology node and beyond. Considering radio frequency (RF) advances, FinFETs have been considered an attractive candidate for high‐frequency applications . To parallel the process technology and circuit design methodology, a compact model that serves as a link between process technology and circuit design is greatly needed.…”