Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels

Deutsch, Sergej; Chakrabarty, Krishnendu

doi:10.7873/date.2013.225

Cited by 27 publications

(14 citation statements)

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“…This value is considered as the reference value for a fault-free TSV in the sequel of this paper. As in [10], the TSV model used for spice simulations is a pure capacitance.…”

Section: B Spice Simulation Resultsmentioning

confidence: 99%

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A 3D IC BIST for pre-bond test of TSVs using ring oscillators

Fkih¹,

Vivet²,

Rouzeyre

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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Abstract-3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 µm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs.

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“…This value is considered as the reference value for a fault-free TSV in the sequel of this paper. As in [10], the TSV model used for spice simulations is a pure capacitance.…”

Section: B Spice Simulation Resultsmentioning

confidence: 99%

“…Due to incomplete filling or micro-voids, the capacitance typically decreases. In [10] an R, L, C model of the TSV is simplified to a pure capacitance model. We consider faulty TSVs to have smaller capacitance than non faulty ones.…”

Section: Tsv Failure Detection Using Ring Oscillatorsmentioning

confidence: 99%

A 3D IC BIST for pre-bond test of TSVs using ring oscillators

Fkih¹,

Vivet²,

Rouzeyre

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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“…Pre-bond TSV testing remains one of the major challenges in a 3D test flow due to the limited access to TSVs [47]. In the following paragraphs, we review several methods for pre-bond TSV test that have been proposed in the literature.…”

Section: Pre-bond Tsv Testmentioning

confidence: 99%

Test and debug solutions for 3D-stacked integrated circuits

Deutsch

Chakrabarty

2015

2015 IEEE International Test Conference (ITC)

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Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. TSVs are small copper or tungsten vias that go vertically through the substrate of a die and provide vertical interconnects to a die stacked on top. TSV-based interconnects have benefits in terms of performance, interconnect density, and power efficiency.Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). A number of challenges associated with 3D test need to be addressed before 3D ICs can become economically viable. This dissertation provides solutions to new challenges related to 3D test content, test access, diagnosis and debug.Test content specific to 3D ICs targets defect that occur during TSV manufacturing and stacking process. One example is the effect of thermo-mechanical stress due to TSV fabrication process on the surrounding logic gates. In this dissertation, we analyze these effects and their consequences for delay testing. We provide quantitative results showing that the use of TSV-stress oblivious circuit models for test generation leads to considerable reduction in delay-test quality. We propose a test flow that uses TSV-stress aware circuit models to improve test quality.Another example of 3D-specific test challenge is the testability of TSVs. In this dissertation, we focus on TSV test prior to die bonding, as access to TSVs is limited at this stage. We propose a non-invasive method for pre-bond TSV test that does iv not require TSV probing. The method uses ring oscillators and duty-cycle detectors in order to detect variations in propagation delay of gates connected to a single-sided TSV. Based on the measured variations, we can diagnose the TSV and predict the size of resistive-open and leakage faults using a regression model based on artificial neural networks. In addition, we exploit different voltage levels to increase the robustness of the test method.In order to efficiently deliver test content to structures under test in a 3D stack, 3D design-for-test (DfT) architectures are needed. In this dissertation, we discuss existing 3D-DfT architectures and their optimization. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time, therefore reducing test cost.Post-silicon debug is a major challenge due to continuously increasing design complexity. Traditional debug methods using signal tracing suffer from the limited capacity of on-chip trace buffers that only allow for signal observation during a short time window. This dissertation proposes a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies. The key idea is to use available on-chip DRAM for trace-data storage, which results in a significant increase of the observation window compared to traditional methods that use trace buffers. ...

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“…However, the fabrication process of TSV occasionally causes defects related to their conductor and insulator, e.g., voids and pin-holes [1][2][3] A void increases the resistance of the corresponding TSV and a pin-hole reduces the resistance between the corresponding TSV and the substrate [3][4][5]. These defects cause variations in the resistance and equivalent capacitance of TSVs those can be modeled as a propagation delay fault [4].…”

Section: Introductionmentioning

confidence: 99%

Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells

Jung¹,

Ansari²,

Kim³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

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Non-Invasive Pre-Bond TSV Test Using Ring Oscillators and Multiple Voltage Levels

Cited by 27 publications

References 0 publications

A 3D IC BIST for pre-bond test of TSVs using ring oscillators

A 3D IC BIST for pre-bond test of TSVs using ring oscillators

Test and debug solutions for 3D-stacked integrated circuits

Efficient Pre-Bond Testing of TSV Defects Based on IEEE std. 1500 Wrapper Cells

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