Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis

Abstract

-Statistical Timing Analysis (SSTA) is a method that calculates circuit delay statistically with process parameter variations, die-to-die (D2D) and within-die (WID) variations. In this paper, we model that WID parameter variations are independent for each cell and line in a chip and D2D variations are governed by one variation on a chip. We propose a new method of computing a full chip delay distribution considering both D2D and WID parameter variations. Experimental results show that the proposed method is more accurate than previous methods on actual chip designs. I IntroductionWith the advent of deep sub-micron technologies, the delay variations caused by process, temperature, voltage drop and cross talk are increasing. Static timing analysis (STA) uses the worst-case corner variations in delay calculation, which means that it calculates the delay assuming that all of the process variations cause each gate to take the largest delay during set-up checking. However, since the random parts of the variations of each gate cannot be worst simultaneously on the same chip statistically, STA is usually optimistic by a large margin, which causes over-estimation in delay calculation, requires excessive delay margin in design phases, and makes the timing closure difficult.Statistical static time analysis (SSTA) handles the random parts of the process variations as probability distributions to calculate the delay statistically. It has been studied over the years [1,2]. Several approaches to model the delay distribution have been proposed, and can be categorized in the following three classes: 1) Gaussian Approach [3,4,5,6] Parameter variations are expressed either as a single normal random variable or a linear sum of normal variables. The delay distribution will be Gaussian. Statistical operations can be executed with less computational penalty, but this approach has a limitation in expressing the non-Gaussian on statistical maximum operations.2) Non-Linear Gaussian Approach [7,8,9] Parameter variations are expressed as a non-linear function of normal random variables. It can express any distributions other than Gaussian. However, the statistical maximum operation contains theoretical errors because it is not closed with respect to statistical operations, and it is time-consuming compared with the Gaussian approach.3) Piecewise Linear Approach [10,11,12] The distributions of parameter variations are expressed in a piecewise linear approximation. It can express any form of distributions, and provide accurate statistical operations if fine intervals are allowed. However, the computational time of the operations increases with the number of intervals.On the other hand, in modeling the delay distribution, it is important to model die-to-die (D2D) parameter variations and within-die (WID) parameter variations separately [1,2]. D2D parameter variations result from lot-to-lot, wafer-to-wafer, and global variations within wafer, and give the same parameter variations to each gate on a chip. WID parameter variations resul...

Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis

“…(1) max and (2) max are the maximum delays of the FUs that execute '+ 1 ' and ' * 1 ,' respectively.…”

“…( (1) + (2) ) is the combined timingyield of the FUs which execute and consecutively (referred to as coupled FUs; otherwise, isolated FUs), and (1) + (2) is the PDF of (1) + (2) .…”

“…In general, the timing constraints of operations and are given by (2) if ( , ) is an arc of DFG, all the input data of are available before the CC in which is scheduled, the output data of is consumed only by in the next CC, and the output data of is not consumed in the next CC. We call such operations coupled operations.…”

“…In the design considering delay variations, the maximumdelays ( max in (1), (1) max , and (2) max in (2)) are varied in a range. The timing-yield of an FU with as its probability distribution function (PDF) of delay is defined as follows.…”

“…However, due to process variation, design margin continues to increase rapidly and conventional deterministic or worst-case timing analysis is no longer able to fully realize the benefit of scaling and integrating. Therefore, addressing the process variation problem will require statistical static timing analysis (SSTA) [2]. Differently from the requirement of 100% timing-yield in conventional design, the basic objective of designs using SSTA is to maximize timing-yield while minimizing design overheads such as area [3] and power [4].…”