Non-disjoint decomposition of logic functions in Reed-Muller spectral domain

Hrynkiewicz, Edward; Kolodzinski, Stefan

doi:10.1109/ddecs.2010.5491764

Cited by 9 publications

(10 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The authors apply the results of their previous works [7,8,10,11] which were extended about specific features valid for multi-output functions. The approach is based on implementation of zero-polarity Reed-Muller spectrum.…”

Section: Discussionmentioning

confidence: 99%

“…The non-specified states of this function should be specified according to the rules presented in [8]. It should be done in such a way to obtain the same sub-spectrums which occur in spectrums of function f 1 and function f 2 .…”

Section: Examplementioning

confidence: 99%

“…Hence It means that requirements for existing Ashenhurst and Curtis disjoint decomposition are not met. Therefore it is necessary to check if non-disjoint Curtis decomposition of f 2 function exists [7,8]. Let us assume that common variables set consists of one element and that this element is taken from the bounded set B.…”

Section: Examplementioning

confidence: 99%

See 2 more Smart Citations

Decomposition of multi-output logic function in Reed-Muller spectral domain

Kolodzinski¹,

Hrynkiewicz

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

Self Cite

View full text Add to dashboard Cite

The paper deals with the problems of decomposition of set of logic functions in Reed-Muller spectral domain. The approach is based on searching of the common sub-functions for as many as possible logic functions. A decomposition is executed in Reed-Muller spectral domain but Reed-Muller spectrum of multi-output logic function does not exist. Therefore the common sub-functions are searched in the form of the same sub-spectrums in Reed-Muller spectrum of each function. For these functions for which a disjoint Ashenhurst or Curtis decomposition does not exist a non-disjoint decomposition is searched. A specification of non specified states is performed to obtain the same subspectrum as exists in spectrum of other functions. The examples show that the approach may be profitable.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Examplementioning

confidence: 99%

See 1 more Smart Citation

Decomposition of multi-output logic function in Reed-Muller spectral domain

Kolodzinski¹,

Hrynkiewicz

2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

Self Cite

View full text Add to dashboard Cite

show abstract

“…Therefore, the essence of searching for non-disjoint decomposition is based on searching for variables that may fulfill the role of bound functions. Non-disjoint decomposition may significantly improve the efficiency of using logic resources [43][44][45]. That is why this is the main topic of many papers.…”

Section: Non-disjoint Decompositionmentioning

confidence: 99%

Decomposition of multi-output functions oriented to configurability of logic blocks

Kubica

Kania

2017

Bulletin of the Polish Academy of Sciences Technical Sciences

View full text Add to dashboard Cite

Abstract. The main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-based FPGA. New elements of the proposed synthesis strategy include: an original method of function decomposition, non-disjoint decomposition, and technology mapping dedicated to configurability of logic blocks. The aim of all of the proposed synthesis approaches is the sharing of appropriately configured logic blocks. Innovation of the methods is based on the way of searching decomposition, which relies on multiple cutting of an MTBDD diagram describing a multi-output function. The essence of the proposed algorithms rests on the method of unicoding dedicated to sharing resources, searching non-disjoint decomposition on the basis of the partition of root tables, and choosing the levels of diagram cutting that will guarantee the best mapping to complex logic blocks. The methods mentioned above were implemented in the MultiDec tool. The efficiency of the analyzed methods was experimentally confirmed by comparing the synthesis results with both academic and commercial tools.Key words: BDD, decomposition, logic synthesis, technology mapping. Decomposition of multi-output functions orientedto configurability of logic blocks There are the methods of function technology mapping in LUT-based FPGA structures in which a classic model of decomposition plays a crucial role. A classic model of decomposition may also be one of the elements of synthesis dedicated to CPLD structures [18][19][20]. In fact, it is the basis of function synthesis reflected in LUT-based FPGA structures. Sometimes, logic synthesis method is targeted at FPGA architectures with specialized embedded memory blocks (EMB) [21,22]. In all cases, decomposition of Boolean functions turns out to be a key problem. Decomposition of multi-output functions leads to better results than decomposition done separately on each single function. It is because of the fact that shared blocks are the result of decomposition of Boolean functions and are used by several single-output functions at the same time. A classic model of decomposition is the basis of a series of decomposition algorithms [5,[23][24][25]. Synthesis methods use various graph algorithms that enable indication of column multiplicity of partition tables or a proper transformation of Boolean functions. Undoubtedly, one of the main advantages of a classic function decomposition is the natural admitting of don't-care states. It is probably the most important element making these methods one of the most effective. In last years, a series of various synthesis

show abstract

“…Some function synthesis algorithms have been proposed in the literature [9][10][11][12], but these algorithms are not suitable for implementing an arbitrary -variable function by the RTD-based universal threshold logic gate (UTLG) [13]. And the algorithm [14] which can implement a three-variable nonthreshold function by UTLGs is relatively complicated, and the implemented circuit structure is also complicated.…”

Section: Introductionmentioning

confidence: 99%

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate

Yao

Yang

et al. 2015

Journal of Applied Mathematics

View full text Add to dashboard Cite

The resonant tunneling device (RTD) has attracted much attention because of its unique negative differential resistance characteristic and its functional versatility and is more suitable for implementing the threshold logic gate. The universal logic gate has become an important unit circuit of digital circuit design because of its powerful logic function, while the threshold logic gate is a suitable unit to design the universal logic gate, but the function synthesis algorithm for the -variable logical function implemented by the RTD-based universal logic gate (UTLG) is relatively deficient. In this paper, three-variable threshold functions are divided into four categories; based on the Reed-Muller expansion, two categories of these are analyzed, and a new decomposition algorithm of the three-variable nonthreshold functions is proposed. The proposed algorithm is simple and the decomposition results can be obtained by looking up the decomposition table. Then, based on the Reed-Muller algebraic system, the arbitrary -variable function can be decomposed into three-variable functions, and a function synthesis algorithm for the -variable logical function implemented by UTLG and XOR2 is proposed, which is a simple programmable implementation.

show abstract

Non-disjoint decomposition of logic functions in Reed-Muller spectral domain

Cited by 9 publications

References 4 publications

Decomposition of multi-output logic function in Reed-Muller spectral domain

Decomposition of multi-output logic function in Reed-Muller spectral domain

Decomposition of multi-output functions oriented to configurability of logic blocks

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate

Contact Info

Product

Resources

About