Noise and power reduction in filters through the use of adjustable biasing

Abstract

A technique that enables the variation of bias currents in a filter without causing disturbances at the output is presented. Thus, the bias current can be kept at the minimum value necessary for the total input signal being processed, reducing the noise and power consumption. To demonstrate this approach, a dynamically biased log-domain filter has been designed in a 0.25-m BiCMOS technology. The chip occupies 0.52 mm 2 . In its quiescent condition, the filter consumes 575 W and has an output noise of 4.4 nA rms. Signal-to-noise ratio greater than 50 dB over 3 decades of input and total harmonic distortion less than 1% for inputs less than 2.5 mA peak are achieved. The bias can be varied to minimize noise and power consumption without disturbing the output. Index Terms-Analog filters, companding, dynamic bias, logdomain.Yannis P. Tsividis

Automatic Gain Control

“…The design of an accurate envelope detector is also critical for the efficient magnitude locked loop (MLL) Q-tuning method used in high-Q high-frequency continuous time filters [31]. Additionally, a new generation of dynamically varying analog circuits need high performance envelope detectors to optimize signal-to-noise ratio and power dissipation, such as dynamic gain scaling (syllabic companding) [32], dynamic impedance scaling [33], dynamic biasing [34] and dynamic structure variation [35]. This section is focused on envelope detectors applied to AGCs in wireless receivers and, more precisely, to feedforward AGCs.…”

“…3.41, specifying transistor sizes, component values and biasing conditions. Rather than using a simple transconductor as in [48,49], we employ a high performance G m -cell based on the same core cell as the PGA proposed in [34]. In this way, with a very compact design, the peak detector exhibits higher linearity at higher frequencies with lower power consumption [50].…”

Baseband Analog Circuits for Software Defined Radio

“…On the other hand, v n,in increases by lowering the capacitance value. This is a principle we want to take advantage of: the power dissipation may indeed be reduced by increasing the noise floor (Krishnapura and Tsividis, 2001;Tsividis et al, 2003;Palaskas et al, 2004;Ozgun et al, 2006). When the load capacitance of an integrator op-amp is reduced, its driving capabilities can be reduced and power savings can thus be achieved by using a proper reconfigurable op-amp together with a programmable array of capacitors.…”

Fast-Settling Envelope Detectors

“…The design of accurate envelope detector is critical for efficient magnitude locked loop (MLL) Q-tuning method used in high-Q highfrequency continuous time filters [4]. A new generation of dynamically varying analog circuit need high performance envelope detectors to optimize signal-to-noise ratio and power dissipation, such as dynamic gain scaling (syllabic companding) [5], dynamic impedance scaling [6], dynamic biasing [7] and dynamic structure variation [8]. The conventional diode-RC peak detector is too simple and low efficient for these applications [9].…”