NoC power optimization using combined routing algorithms

Wu, Ji; Dong, Dezun; Wang, Li

doi:10.1109/icis.2017.7960009

Cited by 6 publications

(1 citation statement)

References 23 publications

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“…The review is performed by considering the researches published in top publication like IEEE Xplore. The work of Wu [11] has designed NoC(Network-on-Chip) power optimization using routing algorithm. Here combined routing algorithm (CRA) is presented with a novel Multi-NoC design with distinct routing algorithms for different subnets.…”

Section: Review Of Literaturementioning

confidence: 99%

Design of Conventional and Modified Router Design for NOC and its FPGA Implementation

Manjunatha¹

2018

CAE

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FPGA Based Systems are helpful improves the performance metrics with high throughput for SOC and NOC Based designs. NOC is an integration of complex-network system into singledevice or a chip. This reduces the manufacturing cost of SOC, increases the performance and reduces the time-consumption. In this paper, two different types of NOC Designs are synthesized and implemented. Firstly, Conventional NOC 2X2 Router includes the 5-channels namely, local, east, north, south and north. Each channel is having 2 Multiplexors along with cross bar switch. Secondly, Proposed NOC 2X2 Router includes 4 Nodes and each Node is having the priority encoder, Random arbiter and router design using XY Algorithms. The proposed designs executing in Xilinx 14.7 and simulated using Modelsim. The outcome of executed scheme gives detailed results with their input and output. The system design is synthesized in Xilinx 14.7 ISE using Verilog and simulated in Modelsim 6.3f and these implemented on FPGA board of version Artix 7. The performance analysis of Proposed NOC 2X2 Router over Conventional NOC 2X2 Router is improves the area overhead and it is tabulated.

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Section: Review Of Literaturementioning

confidence: 99%