NoC Dimensioning from Mathematical Models

Abstract

NoCs (Network-on-Chip) have emerged as efficient scalable and low power communication structures for SoC (System-On-Chip). Two main challenges are pointed out when prototyping a SoC on a reconfigurable chip such as FPGA (Field Programmable Gate Array). The first challenge is to tune a NoC according to the application requirements by exploring all design solutions. The second challenge is to dimension the FPGA resources regarding the previously selected appropriate solution. Usually, dimensioning of FPGA resources is done by several runs of automatic synthesis processes to evaluate if the number of resources fits to the selected FPGA device. Finding the most appropriate solution and FPGA dimensioning are time consuming and the design space exploration is not fully done in order to decrease the exploration time. A more appropriate solution would be analytic models of the NoC on a FPGA device. Mathematical modelling consists in identifying links between the NoC parameters and the FPGA resources using a database and in extracting relations between them. In this paper, we present a methodological framework to estimate the number of resources required for a given communication architecture and the task graph of the application. The framework contains 4 steps: the design or the selection of the NoC, the data collection, the data analysis from which a model is deduced. The database obtained in the data collection step contains the synthesized results of each NoC configuration. Two NoCs, with a mesh topology and different characteristics, are used to provide two databases. The methodological framework provides the most appropriate models that are identified using predictive modelling. The evaluation of each model shows that the relative error is less than 5% in most cases. It is therefore possible to tune the most appropriate NoC and to estimate the required resources in a short exploration time without the synthesis steps.