Niagara-2: A highly threaded server-on-a-chip

Grohoski, Greg

doi:10.1109/hotchips.2006.7477874

Cited by 23 publications

(12 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…We performed our experiments on a 1.4 GHz Sun SPARC Enterprise R T5440 server [6], which combines chip-level multithreading (CMT) and symmetric multiprocessing (SMP) designs. The T5440 server contains four UltraSPARC R T2 Plus processors connected via four UltraSPARC T2 Plus XBR coherency hubs.…”

Section: Methodsmentioning

confidence: 99%

Scalable reader-writer locks

Lev

Luchangco

Olszewski

2009

Proceedings of the Twenty-First Annual Symposium on Parallelism in Algorithms and Architectures

View full text Add to dashboard Cite

We present three new reader-writer lock algorithms that scale under high read-only contention. Many previous reader-writer locks suffer significant degradation when many readers attempt to acquire the lock concurrently, even though they are all allowed to hold the lock at the same time. In contrast, our locks scale almost perfectly when there is only read contention on a 4-chip system with a total of 256 hardware threads.Two of the algorithms extend the MCS queue mutex to provide reader-writer synchronization with low overhead, and can be used when busy-waiting synchronization is appropriate. The third algorithm is an improvement on a production-quality reader-writer lock used in the Solaris TM kernel, which provides robust priority and flexible fairness guarantees.A key tool we developed to implement our reader-writer locks is the closable scalable nonzero indicator (C-SNZI), a variation on the SNZI object. C-SNZI objects allow us to significantly reduce the contention among reads when many readers try to acquire the lock concurrently, but keeps the acquisition overhead small in the absence of read contention. We present an algorithm for C-SNZI that achieves this goal, and show how it can be used by each of our lock algorithms to provide scalable reader-writer locks with different fairness guarantees.

show abstract

Section: Methodsmentioning

confidence: 99%

Scalable reader-writer locks

Lev

Luchangco

Olszewski

2009

Proceedings of the Twenty-First Annual Symposium on Parallelism in Algorithms and Architectures

View full text Add to dashboard Cite

show abstract

“…General-purpose programmable packet processing systems have been developed in form of high-performance, generalpurpose workstation processors (e.g., Sun's Niagara2 platform [10]), network processors (e.g., Intel's IXP platform [19]), and programmable logic devices (e.g., P4 [11] and NetFPGA [15]). In the context of next-generation Internet architecture proposals [7], various router designs have employed specialized hardware to provide programmable packet processing functionality at high data rates (e.g., GENI backbone platforms [21] and high-performance PlanetLab nodes [22]).…”

Section: Related Workmentioning

confidence: 99%

On runtime management in multi-core packet processing systems

Wolf

2008

Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

View full text Add to dashboard Cite

Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing systems on routers employ multiple processor cores. We investigate the design of an efficient run-time management system that handles the allocation of processing tasks to processor cores. Using run-time profiling information about processing requirements and traffic characteristics, the system is able to adapt to dynamic changes in the workload and balance the utilization of all processing resources to maximize throughput. We present a prototype implementation of our system that is based on the Click modular router. Our results show that our prototype system can adapt to changing workloads and process computationally demanding packets at 1.32 times higher data rates than SMP Click.

show abstract

“…The trend of migrating discrete devices and accelerators onto the processor chip has also started in CMPs (Chip-Multiprocessors) [4,5,13,21,41]. Intel's Sandy Bridge includes MPEG4 encoder and decoder, 3D graphics and display controller onto the processor die [5].…”

Section: Introductionmentioning

confidence: 99%

Cost-effectively offering private buffers in SoCs and CMPs

Fang

Zhao

Iyer

et al. 2011

Proceedings of the International Conference on Supercomputing

View full text Add to dashboard Cite

High performance SoCs and CMPs integrate multiple cores and hardware accelerators such as network interface devices and speech recognition engines. Cores make use of SRAM organized as a cache. Accelerators make use of SRAM as special-purpose storage such as FIFOs, scratchpad memory, or other forms of private buffers. Dedicated private buffers provide benefits such as deterministic access, but are highly area inefficient due to the lower average utilization of the total available storage. We propose Buffer-integrated-Caching (BiC), which integrates private buffers and traditional caches into a single shared SRAM block. Much like shared caches improve SRAM utilization on CMPs, the BiC architecture generalizes this advantage for a heterogeneous mix of cores and accelerators in future SoCs and CMPs. We demonstrate cost-effectiveness of the BiC using SoC-based low-power servers and CMP-based servers with on-chip NIC. We show that with a small extra area added to the baseline cache, BiC removes the need for large, dedicated SRAMs, with minimal performance impact.

show abstract

Niagara-2: A highly threaded server-on-a-chip

Cited by 23 publications

References 0 publications

Scalable reader-writer locks

Scalable reader-writer locks

On runtime management in multi-core packet processing systems

Cost-effectively offering private buffers in SoCs and CMPs

Contact Info

Product

Resources

About