2020
DOI: 10.48550/arxiv.2003.00133
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Next-Generation Topology of D-Wave Quantum Processors

Abstract: This paper presents an overview of the topology of D-Wave's nextgeneration quantum processors. It provides examples of minor embeddings and discusses performance of embedding algorithms for the new topology compared to the existing Chimera topology. It also presents some initial performance results for simple, standard Ising model classes of problems.

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Cited by 51 publications
(66 citation statements)
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References 11 publications
(18 reference statements)
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“…For arbitrary graphs without an obvious relation to such a structure, being too large to simply use the complete graph scheme but small enough that they might fit, we always need to find a suitable embedding before we are able to calculate on the machine. This still holds for the new hardware architecture with the Pegasus graph, although it yields a higher connectivity [3].…”
Section: Introductionmentioning
confidence: 97%
See 1 more Smart Citation
“…For arbitrary graphs without an obvious relation to such a structure, being too large to simply use the complete graph scheme but small enough that they might fit, we always need to find a suitable embedding before we are able to calculate on the machine. This still holds for the new hardware architecture with the Pegasus graph, although it yields a higher connectivity [3].…”
Section: Introductionmentioning
confidence: 97%
“…Above we use the term ideal as it refers to the graph provided from the built-in hardware structure of overlapping superconducting loops forming the qubits, which is for instance described in [3]. However, some qubits, or in rare cases also couplings, are switched off by the programming interface of the currently operating hardware, because they do not show the expected behaviour [7].…”
Section: Introductionmentioning
confidence: 99%
“…Increasing both the graph dimensionality of qubit networks [2,30], and improving connectivity [31], the degree to which the qubits are coupled to one another, would greatly reduce physical hardware overhead by increasing the types and sizes of optimization problems that can be natively embedded. Existing quantum annealing processors based on superconducting qubits possess either nearest neighbor [32] or a combination of inter-and intra-unit cell interactions [33] between qubits. Commercial annealers, possessing this combination of inter-and intra-unit cell interactions, currently rely on minor embedding [34,35], a procedure of extending logical qubits over multiple physical qubits to implement problems that require higher dimensionality or connectivity than the processor's hardware natively allows.…”
Section: Introductionmentioning
confidence: 99%
“…Programmable quantum annealers have developed significantly in the last decade and now host thousands of interacting qubits realizing an effective transverse field Hamiltonian [1][2][3] . While these developments are primarily motivated by the hope that such quantum annealers will efficiently solve classical optimization problems, there is accumulating evidence that they may be used to probe the statistical physics of frustrated magnets [4][5][6][7] .…”
mentioning
confidence: 99%